CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.6 CardBus Status
Register Name: CardBus Status
Offset: 14h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Byte 3
CardBus
Status (high)
Address/Data
Parity Error
Detected
RC:0
Bit 23
Received
System Error
(SERR#)
RC:0
Bit 22
Received
Master Abort
RC:0
Bit 21
Received
Target Abort
RC:0
Bit 20
Signalled
Target Abort
RC:0
Bit 19
Byte 2
CardBus
Status (low)
Bit 15
Bit 14
Bit 13
Reserved
R:00000000
Bit 12
Bit 11
Byte 1
Reserved
Register Per: socket
Bit 26
Bit 25
Reserved
R:00
Bit 18
Bit 17
Bit 24
Secondary
Bus Data
Parity Error
Reported
RC:0
Bit 16
Bit 10
Bit 9
Bit 8
Bit 7
Byte 0
Bit 6
R:00000000
Bit 5
Bit 4
Bit 3
Bit 2
Power Capabilities Pointer
Bit 1
Bit 0
R:10000000
NOTE: The CardBus (Secondary) Status bytes are similar to the Status bytes in the Command and Status regis-
ter, but contain information relating to the CardBus. Bit 30 is defined differently than in the Command and
Status register. These bits are reset by PCI reset and by writing ‘1’ to the bit.
Bits 7:0 — Power Capabilities Pointer
This value indicates that the CardBus Controller Power Management registers begin at offset
80h in this configuration space.
Bits 23:8 — Reserved
Bit 24 — Secondary Bus Data Parity Error Reported
This bit is used to report the receipt of PERR# on the PC Card 32 bus. Write a ‘1’ to this bit to clear
it.
Bits 26:25 — Reserved
Bit 27 — Signalled Target Abort
To clear this bit, software must write a ‘1’ to it.
0
No target device has signalled a target abort.
1
A target device has signalled a target abort.
Bit 28 — Received Target Abort
To clear this bit, software must write a ‘1’ to it.
0
No master transaction has been terminated with a target abort.
1
A master transaction has been terminated with a target abort.
June 1998
ADVANCE DATA BOOK v0.3
55
PCI CONFIGURATION REGISTERS
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