CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.10
I/O Base 0–1
Register Name: I/O Base 0–1
Offset: 2Ch, 34h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
I/O Base 31:24
Byte 2
Bit 23
Bit 22
Bit 21
R:00000000
Bit 20
Bit 19
I/O Base 23:16
Bit 18
Bit 17
Bit 16
R:00000000
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Byte 1
I/O Base 15:8
Bit 8
Bit 7
Byte 0
Bit 6
R/W:11111111
Bit 5
Bit 4
Bit 3
I/O Base 7:2
Bit 2
Bit 1
Bit 0
I/O Space Indicator
R/W:111111
R:00
Bits 1:0 — I/O Space Indicator 1:0
These bits are an extension to the I/O Base register and always read back ‘00’. The value ‘00’
indicates that the CL-PD6833 supports 16-bit PCI I/O address decoding. As described in the
PCI-to-CardBus Register description specification, this means I/O access intended for CardBus
cards require PCI address bits 31:16 to be ‘0’.
Bits 15:2 — I/O Base 15:2
These bits define the bottom of an address range of a PCI I/O window to be mapped to a CardBus-
capable PCI I/O space. These bits correspond to PCI I/O address bits 15:2.
Bits 31:16 — I/O Base 31:16
These bits read all ‘0’s to be compatible with the CL-PD6832.
NOTE: I/O Base 0–1 and I/O Limit 0–1 registers are enabled by bit 0 of the Command and Status register. To
disable one window, set the limit of that window below the base. For example, if I/O base is equal to I/O limit,
the CL-PD6833 does doubleword I/O addressing.
60
PCI CONFIGURATION REGISTERS
ADVANCE DATA BOOK v0.3
June 1998
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