CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
5.7 PCI Bus Number, CardBus Number, Subordinate Bus Number, and CardBus
Latency Timer
Register Name: PCI Bus Number, CardBus Number, Subordinate Bus
Number, and CardBus Latency Timer
Offset: 18h
Bit 31
Bit 30
Bit 29
Bit 28
Bit 27
Bit 26
Register Per: socket
Bit 25
Bit 24
Byte 3
CardBus
Latency
Timer
Byte 2
Subordinate
Bus Number
Bit 23
Bit 15
CardBus Latency Timer 7:3
Bit 22
R/W:00000
Bit 21
Bit 20
Bit 19
Bit 14
Bit 13
Subordinate Bus Number
R/W:00000000
Bit 12
Bit 11
CardBus Latency Timer 2:0
Bit 18
R:000
Bit 17
Bit 16
Bit 10
Bit 9
Bit 8
Byte 1
CardBus
Number
Byte 0
PCI Bus
Number
Bit 7
Bit 6
Bit 5
CardBus Number
R/W:00000000
Bit 4
Bit 3
PCI Bus Number
R/W:00000000
Bit 2
Bit 1
Bit 0
Bits 7:0 — PCI Bus Number
This byte identifies the number of the PCI bus on the primary side of the bridge. This byte is set
by PCI BIOS configuration software.
Bits 15:8 — CardBus Number
This byte identifies the number of the CardBus attached to the socket, and it is set by PCI BIOS
configuration software or socket services.
Bits 23:16 — Subordinate Bus Number
This byte is defined for PCI-to-PCI bridges. It identifies the number of the bus at the lowest part of
the hierarchy behind the bridge. Normally, a CardBus bridge is at the bottom of the bus hierarchy
and this register holds the same value as the CardBus Number register.
Bits 31:24 — CardBus Latency Timer 7:0
This byte has the same functionality as the primary PCI Bus Latency Timer, but applies to the
CardBus attached to this specific socket. This byte is set by PCI BIOS configuration software or
socket services.
June 1998
ADVANCE DATA BOOK v0.3
57
PCI CONFIGURATION REGISTERS
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