MCLK
DRA[12:0]
RAS[3:0]
CL-PS7110
Low-Power System-on-a-Chip
DRAM CAS-before-RAS refresh cycle (MCLK shown for reference only)
tCSA
HELD
tRC
tRAS
ROW
COL
CAS[3:0]
D[31:0]
NMOE
HELD
NMWE
Figure 4-6. DRAM CAS-Before-RAS Refresh Cycle
NOTES:
1) tCSA (CAS set-up time) = 25 ns minimum at MCLK = 18.432 MHz
2) tRAS (RAS pulse width) = 80 ns minimum at MCLK = 18.432 MHz
3) tRC (cycle time) = 160 ns minimum at MCLK = 18.432 MHz
4) When DRAMs are placed in self-refresh (entering standby) the same timings apply, but tRAS is extended
indefinitely.
68
ELECTRICAL SPECIFICATIONS
May 1997
DATA BOOK v1.5