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CL-PS7110 View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CL-PS7110
Cirrus-Logic
Cirrus Logic Cirrus-Logic
'CL-PS7110' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
4.5 I/O Buffer Characteristics
All I/O buffers on the CL-PS7110 are CMOS threshold input bidirectional buffers except the oscillator and
power pads. Notional input signals only enable the output buffer during Pin Test mode. All output buffers
are disabled during System Test (High-Z) mode. All buffers have a standard CMOS threshold input stage
apart from the Schmitt inputs and CMOS, slew-rate-controlled output stages to reduce system noise.
Table 4-3 defines the I/O buffer output characteristics.
Table 4-3. I/O Buffer Output Characteristics
Buffer Type
I/O strength 1
I/O strength 2
I/O strength 3
I/O strength 4
Drive Current
± 3 mA
± 3 mA
± 12 mA
± 12 mA
Propagation Delay
(MAX)
15 ns
15 ns
12 ns
12 ns
Rise Time
(MAX)
18 ns
15 ns
15 ns
180 ns
Fall Time
(MAX)
15 ns
15 ns
13 ns
80 ns
Load
50 pF
50 pF
50 pF
1000 pF
NOTE:
1) All propagation delays are specified at 50% VDD to 50% VDD; all rise times are specified as 10% VDD to 90% VDD,
and all fall times are specified as 90% VDD to 10% VDD.
2) Pull-up current = 50 µA typical at VDD = 3.3 volts.
4.6 Test Modes
The CL-PS7110 supports a number of hardware-activated test modes; these are activated by the pin
combinations shown in Table 4-4. All latched signals will only alter test modes while NPOR is low, and
their state is latched on the rising edge of NPOR. This allows these signals be used normally during var-
ious test modes; for example, the NURESET input can be used normally when the device is set into Func-
tional Test (EPB) mode.
Table 4-4. CL-PS7110 Hardware Test Modes
Test Mode
Normal operation (32-bit boot)
Normal operation (8-bit boot)
Alternative test ROM boot
Oscillator/PLL bypass
Functional Test (EPB)
Oscillator/PLL Test
Pin Test
System Test (all High-Z)
Latched
MEDCHG
0
0
1
X
X
X
X
X
Latched
PE0
0
1
X
X
X
X
X
X
Latched
NURESET
X
X
X
X
1
0
1
0
NTEST0 NTEST1
1
1
1
1
1
1
1
0
0
1
0
1
0
0
0
0
70
ELECTRICAL SPECIFICATIONS
May 1997
DATA BOOK v1.5
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