CL-PS7110 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 4-6. Oscillator and PLL Test Mode Signals
Signal
I/O Pin Function
TSELa
XTALONa
PLLONa
DN0
DN1a
PLLBP
RTCCLK
CLK1
OSC36
CLK576K
VTEST
VREF
I
PA5 PLL test select
I
PA4 Enable to oscillator circuit
I
PA3 Enable to PLL circuit
I
PA2 Selects other frequencies from PLL with DN0
I
PA1 Selects other frequencies from PLL with DN1
I
PA0 Bypasses PLL
O COL0 Output of RTC oscillator
O COL1 1-Hz clock from RTC divide chain
O COL2 36-MHz PLL main output
O COL4 576 kHz divided-down as above
O COL5 Analog output of VCO loop filter
O COL6 VCO output for test
a These inputs are INVERTED before being passed to the PLL to ensure that the default state of the port
(all ‘0’) maps onto the correct default state of the PLL (TSEL = 1, XTALON = 1, PLLON = 1, D0 = 0, D1
= 1, PLLBP = 0). This state produces the correct frequencies as shown in Table 4-6. Any other combina-
tions are for testing the oscillator and PLL and should not be used in the circuit.
4.6.4 Pin Test Mode
This mode is selected by NTEST0 = 0, NTEST1 = 0, Latched NURESET = 1.
This test mode allows a simple ICT tester to check if all pins on the CL-PS7110 are correctly soldered to
the PCB. This mode does this by back-driving each pin in turn, and checking the response on one desig-
nated pin (the COL7 pin).
A parity bit is generated and output on the COL7 pin; this parity bit is the XOR of the input from every
CL-PS7110 signal pin except for the two test inputs. The input pad of each signal is fed into this XOR gate
regardless of signal type. Externally driving (back-driving) any signal pin from its reset state causes a tran-
sition of the COL7 pin. Table 4-6 defines the rest state for all CL-PS7110 output pins. As Pin Test mode
is entered, the states of all CL-PS7110 inputs are latched, and forced back out on the pins. Thus ALL pins
(except the two test pins) are configured as outputs in this mode. This ensures only a ‘good’ solder joint
passes the pin test. When not in Pin Test mode, the XOR chain is disabled and cannot toggle to save
power.
It is essential in Pin Test mode that the NURESET pin is kept in the default (HIGH) state except when it
is being tested itself. This ensures that NPOR can be safely included in the pin test chain without affecting
the test mode.
72
ELECTRICAL SPECIFICATIONS
May 1997
DATA BOOK v1.5
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