CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
The CL-PS7110 design is optimized for low power dissipation at 3-V operation. At 18.432-MHz clock
speed, the device dissipates 66 mW during the ‘operating state’ (all oscillators and processor clock run-
ning), 15 mW in the ‘idle state’ (all oscillators running, but processor clock is halted), and 10-µW in the
‘standby state’ (no display and the main oscillator is shut down). For a definition of the three states, refer
to the Section 1.2.19 on page 27.
The CL-PS7110 can interface to up to four banks of DRAM; each bank can be up to 256 Mbytes in size.
There is also an interface for two ROMs, each up to 256 Mbytes, and six expansion devices also up to
256 Mbytes. These expansion devices could be additional ROM or a PC Card controller. The CL-PS7110
has a built-in, high-speed (115 kbps) UART with Rx and Tx FIFOs, and also supports the IrDA SIR proto-
col.
The CL-PS7110 is fabricated with a 0.6-µm CMOS process and is fully static. The CL-PS7110 is a 208-pin
VQFP with a body size of 28-mm square, a lead pitch of 0.5 mm, and a maximum thickness of 1.5 mm.
1.2 General
The CL-PS7110 is built around the ARM710A processor core. For a more detailed description of the
ARM710A, refer to the ARM710A Data Sheet (http://www.arm.com/). The principle functional blocks in
CL-PS7110 are:
q ARM710A CPU core
q Memory management unit from the ARM700 and ARM710 processors
q 8 Kbytes of unified instruction and data cache, plus a four-way set-associative cache controller
q Interrupt and fast interrupt controller
q Expansion and ROM interface giving 8 × 256-Mbyte expansion segments with independent wait state control
q DRAM controller supporting Fast Page mode and self-refresh in Standby mode
q 36 bits of general-purpose peripheral I/O
q Telephony codec interface and 16-byte FIFO
q Programmable, 4-bits-per-pixel LCD controller, mapping the video buffer into the main DRAM
q Full-duplex UART and two 16-byte FIFOs, plus logic to implement the IrDA SIR protocol, capable of speeds
up to 115 kbps
q Two 16-bit general-purpose counter timers
q A 32-bit realtime clock and comparator
q DC-to-DC converter interface
q System state control and power management
q Synchronous serial interface for Microwire® or SPI® peripherals (such as ADCs)
q Pin test and device-isolation logic
q External tracing support for debug
q Main oscillator and PLL (phase locked loop) to generate the system clock of 18.432 MHz from a 3.6864-MHz
crystal
q A low-power 32.768-kHz oscillator
12
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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