CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
Table 1-2. Physical-to-DRAM Address Mapping (cont.)
2
A4
A12
A25/DRA2
3
A5
A13
A24/DRA3
4
A6
A14
A23/DRA4
5
A7
A15
A22/DRA5
6
A8
A16
A21/DRA6
7
A9
A17
A20/DRA7
8
A19
A18
A19/DRA8
9
A21
A20
A18/DRA9
10
A23
A22
A17/DRA10
11
A25
A24
A16/DRA11
12
A27
A26
A15/DRA12
Table 1-3 shows the address mapping for various DRAMs with square and non-square row and address
inputs assuming two ×16 devices are connected to each RAS line. This mapping is then repeated every
256 Mbytes for each DRAM bank. n is given by n = 0xC + bank number (for example, 0xC for bank 0;
0xF for bank 3, etc.).
Table 1-3. DRAM Address Mapping
Device
Size
4 Mbits
16 Mbits
Address
Configuration
9 Row × 9 Column
10 Row × 10 Column
Total Size
of Bank
1 Mbyte
4 Mbytes
16 Mbits
12 Row × 8 Column
4 Mbytes
64 Mbits
11 Row × 11 Column
16 Mbytes
64 Mbits
13 Row × 9 Column
16 Mbytes
256 Mbits
1 Gbit
12 Row × 12 Column
13 Row × 13 Column
64 Mbytes
256 Mbytes
Address Range of
Segment(s)
n000.0000–n00F.FFFF
n000.0000–n03F.FFFF
n000.0000– n007.FFFF
n010.0000–n017.FFFF
n040.0000–n047.FFFF
n050.0000–n057.FFFF
n100.0000–n107.FFFF
n110.0000–n117.FFFF
n140.0000–n147.FFFF
n150.0000–n157.FFFF
n000.0000–n0FF.FFFF
n000.0000–n01F.FFFF
n040.0000–n05F.FFFF
n100.0000–n11F.FFFF
n140.0000–n15F.FFFF
n400.0000–n41F.FFFF
n440.0000–n45F.FFFF
n500.0000–n51F.FFFF
n540.0000–n55F.FFFF
n000.0000–n3FF.FFFF
n000.0000–nFFF.FFFF
Size of
Segment(s)
1 Mbyte
4 Mbytes
512 Kbytes
16 Mbytes
2 Mbytes
64 Mbytes
256 Mbytes
20
FUNCTIONAL DESCRIPTION
May 1997
DATA BOOK v1.5
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