CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
EINT2
EINT3
TC1OI
TC2OI
RTCMI
TINT
UTXINT
URXINT
UMSINT
SSEOTI
External interrupt input 2. This interrupt is active if the NEINT2 input is active (low). It
is cleared by returning NEINT2 to the passive (high) state.
External interrupt input 3. This interrupt is active if the EINT3 input is active (high) it
is cleared by returning EINT3 to the passive (low) state.
TC1 under-flow interrupt. This interrupt becomes active on the next falling edge of
the timer counter 1 clock after the timer counter has under-flowed (reached ‘0’). It is
cleared by writing to the TC1EOI location.
TC2 under-flow interrupt. This interrupt becomes active on the next falling edge of
the timer counter 2 clock after the timer counter has under-flowed (reached ‘0’). It is
cleared by writing to the TC2EOI location.
RTC compare match interrupt. This interrupt becomes active on the next rising edge
of the 1-Hz realtime clock (one second later) after the 32-bit time written to the real-
time clock match register exactly matches the current time in the RTC. It is cleared by
writing to the RTCEOI location.
64-Hz tick interrupt. This interrupt becomes active on every rising edge of the internal
64-Hz clock signal. This 64-Hz clock is derived from the 15-stage ripple counter that
divides the 32.768-kHz oscillator input down to 1 Hz for the realtime clock. This inter-
rupt is cleared by writing to the TEOI location.
Internal UART transmit FIFO half-empty interrupt. The function of this interrupt
source depends on whether the UART FIFO is enabled. If the FIFO is disabled
(FIFOEN bit is clear in the UART Bit Rate and Line Control register), this interrupt is
active when there is no data in the UART Tx Data Holding register, and cleared by
writing to the UART Data register. If the FIFO is enabled this interrupt is active when
the UART Tx FIFO is half or more empty, and is cleared by filling the FIFO to at least
half full.
Internal UART receive FIFO half-full interrupt. The function of this interrupt source
depends on whether the UART FIFO is enabled. If the FIFO is disabled this interrupt
is active when there is valid Rx data in the UART Rx Data Holding register, and is
cleared by reading this data. If the FIFO is enabled this interrupt is active when the
UART Rx FIFO is half or more full or if the FIFO is non empty and no more characters
are received for a 3-character time-out period. It is cleared by reading all the data from
the Rx FIFO.
Internal UART modem status changed interrupt. This interrupt is active if either of the
two modem status lines (CTS or DSR) change state. It is cleared by writing to the
UMSEOI location.
Synchronous serial interface end-of-transfer interrupt. This interrupt is active after a
complete data transfer to and from the external ADC has completed. It is cleared by
reading the ADC data from the SYNCIO register.
May 1997
DATA BOOK v1.5
51
PROGRAMMING INTERFACE
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