CL-PS7110-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CL-PS7110-VC-A' PDF : 82 Pages View PDF
CL-PS7110
Low-Power System-on-a-Chip
3.2.23 PMPCON — Pump Control Register
The DC-to-DC Converter Pump Control register is a 12-bit read/write-only register that sets and controls
the variable mark space ratio drives for two DC-to-DC converters. All bits in this register are cleared by a
system reset.
11
Drive 1 pump ratio
87
43
0
Drive 0 from mains ratio
Drive 0 from battery ratio
Drive 0 from battery This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system
is powered from batteries. Setting these bits to ‘0’ disables this pump, setting these
bits to ‘1’ allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc.,
up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz. The
NEXTPWR input is used to switch between the two on times for ‘drive0’.
Drive 0 from mains
This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system
is powered from mains (the DC jack input). Setting these bits to ‘0’ disables this pump;
setting these bits to ‘1’ allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16
duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of
96 kHz. The NEXTPWR input switches between the two on times for drive 0.
Drive 1 pump ratio
This 4-bit field controls the on time for the drive 1 DC-to-DC pump. Setting these bits
to ‘0’ disables this pump, setting these bits to ‘1’ allows the pump to be driven in a 1:16
duty ratio, 2 in a 2:16 duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results
in a square wave of 96 kHz.
The state of the output drive pins is latched during power on reset, this latched value is used to determine
the polarity of the drive output. The sense of the DC-to-DC converter control lines is summarized in
Table 3-11.
Table 3-11. Sense of DC-to-DC Converter Control Lines
Initial State of Drive ‘n’ during
POR
Low
High
Sense of Drive ‘n’
Active high
Active low
Polarity of Bias Voltage
+VE
-VE
3.2.24 CODR — Codec Interface Data Register
The CODR register is an 8-bit read/write register. Data written to or read from this register is pushed or
popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is then serialized and sent to or
received from the codec sound device. The codec interrupt CSINT is generated repetitively at 1/8th of the
byte transfer rate and the state of the FIFOs can be read in the System Flags register. The net data trans-
fer rate to/from the codec device is 8 Kbytes per second giving an interrupt rate of 1 kHz.
54
PROGRAMMING INTERFACE
May 1997
DATA BOOK v1.5
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