CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
Part Name
Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
Table 17. Content of I-CODE1 startup configuration
EEPROM
byte
address
Register Value
address
Symbol
30h
10h
00h Page
31h
11h
58h TxControl
32h
12h
3Fh CwConductance
33h
13h
05h ModGsCfgh
34h
14h
2Ch CoderControl
35h
15h
3Fh ModWidth
36h
16h
3Fh ModWidthSOF
37h
17h
00h TypeBFraming
38h
18h
00h Page
39h
19h
8Bh RxControl1
3Ah
1Ah
00h DecoderControl
3Bh
1Bh
54h BitPhase
3Ch
1Ch
68h RxThreshold:
3Dh
1Dh
00h BPSKDemControl
3Eh
1Eh
41h RxControl2
3Fh
1Fh
00h ClockQControl
40h
20h
00h Page
41h
21h
08h RxWait
42h
22h
0Ch ChannelRedundancy
43h
23h
FEh CRCPresetLSB
44h
24h
FFh CRCPresetMSB
45h
25h
00h TimeSlot Period
46h
26h
00h MFOUTSelect
47h
27h
00h PreSet27
48h
28h
00h Page
49h
29h
3Eh FIFOLevel
4Ah
2Ah
0Bh TimerClock
4Bh
2Bh
02h TimerControl
4Ch
2Ch
00h TimerReload
4Dh
2Dh
02h IRQPinConfig
4Eh
2Eh
00h PreSet2E
4Fh
2Fh
00h PreSet2F
Description
free for user
transmitter pins TX1 and TX2 switched off, bridge driver
configuration, modulator driven from internal digital circuitry
source resistance (RS) of TX1 and TX2 to minimum
source resistance (RS) of TX1 and TX2 at the time of
modulation, to determine the modulation index
selects the bit coding mode and the framing during
transmission
pulse width for code used (1 out of 256, NRZ or 1 out of 4)
pulse coding is set to standard configuration
pulse width of SOF
-
free for user
amplifier gain is maximum
bit-collisions always evaluate to HIGH in the data bit stream
BitPhase[7:0] is set to standard configuration
MinLevel[3:0] and CollLevel[3:0] are set to maximum
-
use Q-clock for the receiver, automatic receiver off is
switched on, decoder is driven from internal analog circuitry
automatic Q-clock calibration is switched on
free for user
frame guard time is set to eight bit-clocks
channel redundancy is set using I-CODE1
CRC preset value is set using I-CODE1
CRC preset value is set using I-CODE1
defines the time for the I-CODE1 time slots
pin MFOUT is set LOW
-
free for user
WaterLevel[5:0] FIFO buffer warning level is set to standard
configuration
TPreScaler[4:0] is set to standard configuration, timer unit
restart function is switched off
Timer is started at the end of transmission, stopped at the
beginning of reception
the timer unit preset value is set to standard configuration
pin IRQ is set to high-impedance
-
-
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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