CLRC63201T View Datasheet(PDF) - NXP Semiconductors.
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Description
MFG CO.
'CLRC63201T' PDF : 127 Pages View PDF
NXP Semiconductors
CLRC632
Standard multi-protocol reader solution
9.3 FIFO buffer
An 8 64 bit FIFO buffer is used in the CLRC632 to act as a parallel-to-parallel converter.
It buffers both the input and output data streams between the microprocessor and the
internal circuitry of the CLRC632. This makes it possible to manage data streams up to 64
bytes long without needing to take timing constraints into account.
9.3.1 Accessing the FIFO buffer
9.3.1.1 Access rules
The FIFO buffer input and output data bus is connected to the FIFOData register. Writing
to this register stores one byte in the FIFO buffer and increments the FIFO buffer write
pointer. Reading from this register shows the FIFO buffer contents stored at the FIFO
buffer read pointer and increments the FIFO buffer read pointer. The distance between the
write and read pointer can be obtained by reading the FIFOLength register.
When the microprocessor starts a command, the CLRC632 can still access the FIFO
buffer while the command is running. Only one FIFO buffer has been implemented which
is used for input and output. Therefore, the microprocessor must ensure that there are no
inadvertent FIFO buffer accesses. Table 18 gives an overview of FIFO buffer access
during command processing.
Table 18. FIFO buffer access
Active
command
FIFO buffer
p Write p Read
StartUp
-
-
Idle
-
-
Transmit
yes
-
Receive
-
yes
Transceive
yes
yes
WriteE2
yes
-
ReadE2
yes
yes
LoadKeyE2
yes
-
LoadKey
yes
-
Authent1
yes
-
Authent2
-
-
LoadConfig
yes
-
CalcCRC
yes
-
Remark
the microprocessor has to know the state of the
command (transmitting or receiving)
the microprocessor has to prepare the arguments,
afterwards only reading is allowed
9.3.2 Controlling the FIFO buffer
In addition to writing to and reading from the FIFO buffer, the FIFO buffer pointers can be
reset using the FlushFIFO bit. This changes the FIFOLength[6:0] value to zero, bit
FIFOOvfl is cleared and the stored bytes are no longer accessible. This enables the FIFO
buffer to be written with another 64 bytes of data.
CLRC632
Product data sheet
COMPANY PUBLIC
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 27 February 2014
073937
© NXP Semiconductors N.V. 2014. All rights reserved.
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