CMX838 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
CMX838
4.3.4 Lock Detect Output
The Lock detect status is active high when the phase error corresponds to a time difference of less than about
20ns, 40ns, 60ns, or 80ns at the phase detector comparison inputs. The comparison period is chosen using
the Lock Delay bits of the Channel Select Register ($8B). The lock status is updated according to the lock
detect mode chosen using the Synthesizer General Control Register ($8A). Lock detect data is collected once
every period of the reference signal.
4.3.5 Reference Circuits
The input from the external crystal oscillator is buffered and amplified to CMOS levels. This reference signal is
then divided in frequency by a 12-Bit programmable counter.
The Reference Divider is loaded from a ROM that yields one of four possible reference frequencies: 6.25kHz,
12.5kHz, 20kHz, and 25kHz. Frequency selection is dependent on the RF service bits of the Synthesizer
General Control Register ($8A) or two of the channel select bits when generic RF service is chosen ($8B).
4.4 Baseband Timing Generation
Internal baseband timing is developed from a configurable choice of two sources: a crystal clock signal
(XTAL/CLOCK) or an externally applied synthesizer reference clock signal (REFIN). An on-chip crystal
oscillator amplifier is provided to form a crystal oscillator via the addition of an external crystal.
Several frequency options are supported for both crystal and synthesizer clock source options.
Configuration details are described in Section 5.1.2.7.
2003 CML Microsystems Plc
27
D/838/8
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