CMX838 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
CMX838
5.1.2.2 SETUP Register ($80)
TRANSMIT/
RECEIVE
( TX/RX )
Bit 7
AUDIO INPUT 1
SELECT
Bit 6 and Bit 5
In the Audio section, this bit controls a single pole single throw switch in the audio path
between the deviation limiter/low-pass filter and the transmit modulation digitally
controlled amplifiers. A logic ‘1’ allows audio to flow between these blocks. In the
synthesizer section, this bit in conjunction with the synthesizer intermediate frequency
offset register (SIFOS register) allows for autonomous switching between two
synthesizer frequencies (for example where the required receive frequency equals the
transmit center frequency offset high or low by the radios first intermediate frequency).
A logic ‘1’ will enables synthesis of the transmit frequency, while a logic ‘0’ enables the
offset frequency. In the subaudio section, this bit enables the subaudio encoder
(logic ‘1’) or decoder (logic ‘0’).
A 3-1 mux allows audio to be selected from the microphone amplifier output, the
receive input, or the auxiliary input. Reference Figure 3.
Bit 6
0
1
0
1
Bit 5
0
0
1
1
No inputs selected.
AUX I/O
RXIN
MICOUT
Result
AUDIO INPUT 2
SELECT
Bit 4 and Bit 3
A 3-1 mux allows audio to be selected from AIN (external input), BIN (external input), or
the internal high-pass filter output. The external inputs are available for external audio
processing such as companding and voice scrambling. Reference Figure 3.
Bit 4
0
1
0
1
Bit 3
0
0
1
1
No inputs selected.
AIN
BIN
HPF OUT
Result
AUDIO OUTPUT
SELECT
Bit 2 and Bit 1
A 3-1 mux allows audio to be directed to AOUT (external output), BOUT (external output),
or to the internal deviation limiter/low-pass filter. The external outputs are available for
external audio processing such as companding and voice scrambling. Reference
Figure 3
Bit 0
Bit 2
0
1
0
1
Bit 1
0
0
1
1
Result
No Outputs active, AOUT and BOUT are held at VDD/2
AOUT selected, BOUT held at VDD/2.
BOUT selected, AOUT held at VDD/2
LPF/LIM INPUT
Unused, must be set to logic 0
Table 6: SETUP Register ($80)
2003 CML Microsystems Plc
31
D/838/8
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