CMX838 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
5.1.2.11 SYNTHESIZER 1ST IF OFFSET Register ($8D)
CMX838
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
If RF Service SYNTHESIZER GENERAL CONTROL Register ($8A) Bits D1 and D0 are set to
FRS (=0), PMR 446 (=1) or GMRS (=2).
These 16 bits represent a signed binary number for the offset from the TX frequency to mix down
to the first IF.
The synthesizer will automatically offset the synthesized frequency when the General Control
Register TX bit is clear. The offset will be equal to:
Synthesizer IF Offset (SIFOS) x Reference Oscillator Frequency (SYNTHREF)
Note, SYNTHREF is selected by the RF service control bits of the Synthesizer General Control
Register and SIFOS is a 16 bit signed number formed by bits D[15:0]
D[15:0] = (IF frequency offset)/ SYNTHREF
For example for a high side IF of 21.4MHz
D[15:0] = 1712 (06B0 hex) for FRS and GMRS
D[15:0] = 3424 (0D60 hex) for PMR 446
For a low side IF of 45MHz
D[15:0] = -3600 (F1F0 hex) for FRS and GMRS
D[15:0] = -7200 (E3E0 hex) for PMR 446
M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 A4 A3 A2 A1 A0
If generic system RF service is selected, Synthesizer General Control Register
($8A: D1= 1, D0 = 1); then the RF divider is directly programmed via Synthesizer Channel Select
Register ($8B):D0=M11, SIFOS:D[15:5] = M[10:0], and SIFOS:D[4:0] = A[4:0]
RF divider N = 32 x M[11:0] + A[4:0]
In the Generic Service mode this register must be reloaded to switch between RX and TX to
account for the first IF Offset.
The Synthesized Frequency will be
N x SYNTHREF
where SYNTHREF is set via Synthesizer Channel Select Register ($8B):D[2:1] = R[1:0]. Note the
register Synthesizer Baseband Clock Control must also be set properly for the SYNTHREF to come
out right.
5.1.2.12 16 BIT SUBAUDIO TASK DATA Register ($8E)
Bit(s)
Bit 15-0
Description
This register is used to download 16 bit initialization/configuration data to the tone
signaling processor. Refer to section 4.2.4 for task descriptions.
Table 15: 16 BIT SUBAUDIO TASK DATA Register ($8E)
5.1.2.13 16 BIT SUBAUDIO TEST DATA Register ($8F)
Bit(s)
Bit 15-0
Description
This register is reserved for device test modes.
Table 16: 16 BIT SUBAUDIO TEST DATA Register ($8F)
5.1.2.14 SYNTHESIZER TEST Register ($90)
Bit(s)
Bit 7-0
Description
This register is reserved for device test modes.
Table 17: SYNTHESIZER TEST Register ($90)
2003 CML Microsystems Plc
40
D/838/8
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