CMX838 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
5.1.2.9 SYNTHESIZER CHANNEL SELECT Register ($8B)
Bit 7 and Bit 6
LOCK DETECT
WINDOW
Bit 5 and Bit 4
Always set these two bits to logic 0.
D5 D4
Description
0
0 Lock Detect Comparison Window Set to ±20ns
0
1 Lock Detect Comparison Window Set to ±40ns
1
0 Lock Detect Comparison Window Set to ±60ns
1
1 Lock Detect Comparison Window Set to ±80ns
CHANNEL
SELECT
Bit 3-0
REFERENCE
DIVIDER for
Generic Service
Mode
Bit 3-0
See Note 2
RF CARRIER FREQUENCY (MHz)
D3 D2 D1 D0
FRS
PMR 446
GMRS
See Note 1 See Note 2 See Note 3
0
0
0
0
N/A
N/A
N/A
0
0
0
1
462.5625 446.00625 462.5500
0
0
1
0
462.5875 446.01875 462.5625
0
0
1
1
462.6125 446.03125 462.5750
0
1
0
0
462.6375 446.04375 462.5875
0
1
0
1
462.6625 446.05625 462.6000
0
1
1
0
462.6875 446.06875 462.6125
0
1
1
1
462.7125 446.08125 462.6250
1
0
0
0
467.5625 446.09375 462.6375
1
0
0
1
467.5875
N/A
462.6500
1
0
1
0
467.6125
N/A
462.6625
1
0
1
1
467.6375
N/A
462.6750
1
1
0
0
467.6625
N/A
462.6875
1
1
0
1
467.6875
N/A
462.7000
1
1
1
0
467.7125
N/A
462.71250
1
1
1
1
N/A
N/A
462.72500
Note 1: $8A (D1 = 0, D0 = 0)
Note 2: $8A (D1 = 0, D0 = 1)
Note 3: $8A (D1 = 1, D0 = 0)
D3 D2 D1
D0
Reference Divider output frequency (kHz)
0
0
0
6.25
0
0
0
1
1
0
See Note 1
12.5
20.0
0
1
1
25.0
Note 1: See Register $8D
Note 2: This section is used if Register $8A (D1 = 1, D0 = 1)
CMX838
Table 14: SYNTHESIZER CHANNEL SELECT Register ($8B)
5.1.2.10 SYNTHESIZER STATUS Register ($8C)
This read register stores the lock detect status of the most recent 7 phase comparisons and the current state
of the lock detect circuitry. Refer to the Synthesizer General Control Register ($8A) for information on Lock
Detect Control and IRQ behavior. D0 is the most recent comparison D6 is the least recent, and D7 is the
current state.
2003 CML Microsystems Plc
39
D/838/8
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