CMX838 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX838' PDF : 71 Pages View PDF
FRS/PMR446/GMRS Family Radio Processor
5.1.2.8 SYNTHESIZER GENERAL CONTROL Register ($8A)
CMX838
SYNTHESIZER
POWER
CONTROL
Bit 7 and Bit 6
D7 D6 Description
0
0 Synthesizer is powered down
0
1 Synthesizer is enabled.
1
0 Synthesizer Reference Clock Buffer is powered -
the remainder of the Synthesizer is powered down.
1
1 Reserved for Test Mode.
LOCK CONTROL
Bit 5 and Bit 4
D5 D4 Description
0
0 Lock Detect IRQ is masked
0
1 Lock Detect IRQ is enabled (status updated every phase
comparison when the last two comparisons disagree)
1
0 Lock Detect IRQ is enabled (IRQ updated instantly for loss of
lock, IRQ updated after 8 consecutive in-lock phase compares to
indicate lock)
1
1 Lock Detect IRQ is enabled (IRQ updated after 4 out of lock
comparisons during the last 8, IRQ updated after 16 consecutive
in-lock phase compares to indicate lock).
IHL
Bit 3
POLARITY OF
CHARGE PUMP
OUTPUT
Bit 2
RF SERVICE
Bit 1 and Bit 0
Reference Section 4.3.3 Phase Detector and Charge Pump
D3 Description
0
ICHP = 40 ISET
1
ICHP = 80 ISET
D2
Description
0 Negative VCO V/F slope
1 Positive VCO V/F slope)
D1 D0
Description
0
0 Select FRS channels (SYNTHREF = 12.5kHz )
0
1 Select PMR 446 channels (SYNTHREF = 6.25kHz)
Select GMSR channels (SYNTHREF = 12.5kHz )
1
0 (this does not include the upper frequency band of GMRS which is
reserved for duplex operation in a GMRS system)
1
1 Generic System (RF and Reference Dividers are Directly programmed)
Table 13: SYNTHESIZER GENERAL CONTROL Register ($8A)
2003 CML Microsystems Plc
38
D/838/8
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