COM90C66LJP View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
'COM90C66LJP' PDF : 76 Pages View PDF
DATA SHEET ERRATA FOR REVISION B COM90C66
PAGE
4
13
20,21,
25,37,
39
31-33
34,36
37,40
40
41
48
59
SECTION/FIGURE/ENTRY
CORRECTION
Description of Pin Functions - n0WS Make no connection to this pin.
Figure 2 - Bus Interface
16-Bit Interface Signals must always be present.
The n0WS signal should be left disconnected.
Tables 3, 4, 8 - Configuration Bit 7 (16-Bit Enable) of the Configuration
Register Bit 7 (16EN) and Bit 5 Register must be written to as a logic "1" for
(DECODE); Tables 11, 12; Figure 12 proper device operation. Bit 5 of the
Configuration Register (Decode Mode) is not
effective.
Command Chaining section
The status bits are only single-level.
READ AND WRITE CYCLES -
Memory vs. I/O Cycles section
In I/O Mapped Mode, packets in the internal
RAM buffer must be accessed by addressing
one 16-bit I/O location. The device in 16-bit
mode increments the pointer by two. The device
should not be used in 8-bit mode.
Wait State Details section; Table 13
The Wait State bit may be written to as a logic
"0" to avoid IOCHRDY negation, but the n0WS
signal must be left disconnected.
8-Bit vs. 16-Bit Accesses section
Disregard references to 8-bit Memory and 8-bit
I/O Mapped Mode. All accesses to internal
memory should be 16-bit. When the device is in
16-bit I/O Mapped Mode, byte writes to odd
locations should not be done.
Table 14
8-bit I/O accesses to the Data Register and 8-bit
Memory accesses should not be done.
Figure 14
Disregard the n0WS timing signal. This signal
should not be used.
Figure 26
t3 should read 314 µsec minimum.
63
Share Link: 
