COM90C66LJP View Datasheet(PDF) - SMSC -> Microchip

Part Name

Description

MFG CO.

COM90C66LJP

ARCNET® Controller/Transceiver with AT® Interface and On-Chip RAM

SMSC -> Microchip 

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PAGE

SECTION/FIGURE/ENTRY

CORRECTION

49, 50, 53

Figures 15,16,19 - Read RAM Cycle,

Write RAM Cycle, Read PROM Cycle

For Revision D, a new timing parameter should

exist: Address, SBHE hold after Control

Low...20 nsec minimum. This parameter is only

required if the BALE signal is tied high or left

disconnected.

68

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