CS42L56 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L56' PDF : 92 Pages View PDF
CS42L56
6. REGISTER DESCRIPTION
All registers are read/write except for the chip I.D. and revision register and the status register which are read only.
See the following bit definition tables for bit assignment information. The default state of each bit after a power-up
sequence or reset is listed in each bit description. Unless otherwise specified, all “Reserved” bits must maintain their
default value.
I²C Address: 1001010[R/W]
6.1 Device I.D. Register (Address 01h) (Read Only)
7
DEVID7
6
DEVID6
5
DEVID5
4
DEVID4
3
DEVID3
2
DEVID2
1
DEVID1
0
DEVID0
6.1.1
Device I.D. (Read Only)
Device I.D. code for the CS42L56.
DEVID[7:0]
01010110
Part Number
CS42L56
6.2 Device Revision Register (Address 02h) (Read Only)
7
Reserved
6
Reserved
5
Reserved
4
AREVID2
3
AREVID1
2
AREVID0
6.2.1
Alpha Revision (Read Only)
CS42L56 alpha revision level.
AREVID[2:0]
000
Alpha Revision Level
A
1
MTLREVID1
0
MTLREVID0
6.2.2
Numeric Revision (Read Only)
CS42L56 numeric revision level.
MTLREVID[1:0] Metal Revision Level
00
0
6.3 Power Control 1 (Address 03h)
7
Reserved
6
Reserved
5
PDN_VBUF
4
PDN_BIAS
3
PDN_CHRG
2
PDN_ADCB
1
PDN_ADCA
0
PDN
6.3.1
Power Down VCM Bias Buffer
Configures the power state of the weak internal VCM buffer.
PDN_VBUF
0
1
Application:
Weak VCM Status
All weak VCM buffers for the AINx inputs that are not selected (either through ADCxMUX[1:0] or PGAx-
MUX[1:0]) are powered up. The weak VCM buffers for the AINx inputs that are selected are powered down.
All weak VCM buffers are powered down.
“Optional VCM Buffer” on page 35
DS851F2
57
Share Link: 
