CS42L56 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS42L56' PDF : 92 Pages View PDF
6.5.5
MCLK Divide
Configures a divide of the MCLK after the MCLK pre-divide.
MCLKDIV2
0
1
Application:
MCLK signal into CODEC
No divide
Divided by 2
“Serial Port Clocking” on page 47
CS42L56
6.5.6
MCLK Disable
Configures the MCLK signal prior to all internal circuitry.
MCLKDIS
0
1
MCLK signal into CODEC
On
Off; Disables the clock tree to save power when the CODEC is powered down.
Note: This function should be enabled during power down (PDN=1) ONLY.
6.6 Clocking Control 2 (Address 06h)
7
Reserved
6
Reserved
5
AUTO
4
RATIO4
3
RATIO3
2
RATIO2
1
RATIO1
0
RATIO0
6.6.1
Clock Ratio Auto-Detect
Configures the power status of the Auto-Detect circuitry. When enabled, the Auto-Detect circuitry detects
when the LRCK changes and automatically adjusts internal clock divide-ratios eliminating the need of a
register write to account for the change. It should be noted that the Auto-detect circuitry can only detect
when the LRCK changes by a factor of two while the MCLK stays the same (for instance, Mclk = 6.000
MHz; LRCK changes from 48 kHz to 24 kHz). Any other major clock frequency changes must be account-
ed for by appropriate control port writes.
AUTO
0
1
Application:
Auto-detection of Clock Ratio
Disabled
Enabled
“Serial Port Clocking” on page 47
Note: When AUTO is enabled, the MCLK/LRCK ratio must be implemented according to Table 3 on
page 47.
60
DS851F2
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