CS4398-CZZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4398-CZZ' PDF : 46 Pages View PDF
CS4398
Mode
(sample-
rate range)
Sample
Rate
(kHz)
MCLK (MHz)
MCLKDIV2
MCLKDIV3
MCLK Ratio
256x
384x
512x
768x
1024x
1152x
Single-Speed
(32 to 50 kHz)
32
44.1
8.1920
11.2896
12.2880
16.9344
16.3840
22.5792
24.5760
33.8688
32.7680
45.1584
36.8640
-
48
12.2880 18.4320
24.5760
36.8640
49.1520
-
MCLK Ratio
128x
192x
256x
384x
512x
-
Double-Speed
64
8.1920 12.2880 16.3840 24.5760 32.7680
-
(50 to 100 kHz)
88.2
11.2896 16.9344
22.5792 33.8688 45.1584
-
96
12.2880 18.4320
24.5760
36.8640
49.1520
-
MCLK Ratio
64x*
96x
128x
192x
256x
-
Quad-Speed
176.4 11.2896* 16.9344 22.5792 33.8688 45.1584
-
(100 to 200 kHz)
192
12.2880* 18.4320
24.5760
36.8640 49.1520
-
These modes are only available in Control Port mode by setting the appropriate MCLKDIV bit.
* This MCLK ratio limits the audio word length to 16 bits; see Table 1 on page 21
Table 2. Common Clock Frequencies
4.6 Stand-alone Mode Settings
In Stand-Alone mode (also referred to as “Hardware mode”) the device is configured using the M0 through
M3 pins. These pins must be connected to either the VLC supply or ground. The Interface format is set by
pins M0 and M1. The sample rate range/oversampling mode (Single/Double/Quad-Speed mode) and de-
emphasis are set by pins M2 and M3. The settings can be found in Tables 3 and 4.
M1
M0
0
0
0
1
1
0
1
1
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit Data
Right-Justified, 24-bit Data
Format
0
1
2
3
Figure
3
4
5
5
Table 3. Digital Interface Format, Stand-Alone Mode Options
M3
M2
Description
0
0
Single-Speed without De-Emphasis (32 to 50 kHz sample rates)
0
1
Single-Speed with 44.1 kHz De-Emphasis; see Figure 17 on page 30
1
0
Double-Speed (50 to 100 kHz sample rates)
1
1
Quad-Speed (100 to 200 kHz sample rates)
Table 4. Mode Selection, Stand-Alone Mode Options
The following features are always enabled in Stand-Alone mode: Auto-mute on zero data, Auto MUTEC po-
larity detect, ramp volume from mute to 0dB by 1/8th dB steps every LRCK (soft ramp) after reset or clock
mode change, and the fast roll-off interpolation filter is used.
The following features are not available in Stand-Alone mode: DSD mode, Right-Justified 20- and 18-bit se-
rial audio interfaces, MCLK divide-by-2 and MCLK divide-by-3 (allows 1024 and 1152 clock ratios), slow roll-
off interpolation filter, volume control, ATAPI mixing, 48 kHz and 32 kHz de-emphasis, and all other features
enabled by registers that are not mentioned above.
22
DS568F1
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