CS4398-CZZ View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS4398-CZZ' PDF : 46 Pages View PDF
7. REGISTER DESCRIPTION
** All register access is R/W unless specified otherwise**
CS4398
7.1 Chip ID - Register 01h
7
PART4
0
6
PART3
1
5
PART2
1
4
PART1
1
3
PART0
0
2
REV2
-
1
REV1
-
0
REV0
-
Function:
This register is Read-Only. Bits 7 through 3 are the part number ID, which is 01110b (14h), and the remain-
ing Bits (2 through 0) are for the chip revision (Rev. A = 000, Rev. B = 001, ...)
7.2 Mode Control 1 - Register 02h
7
DSD_SRC
0
6
DIF2
0
5
DIF1
0
4
DIF0
0
3
DEM1
0
2
DEM0
0
1
FM1
0
0
FM0
0
7.2.1
DSD Input Source Select (DSD_SRC) BIT 7
Function:
When set to 0 (default), the dedicated DSD pins will be the active DSD inputs.
When set to 1, the source for DSD inputs will be as follows:
DSDA input on SDATA pin
DSDB input on LRCK pin
DSD_SCLK input on SCLK pin
The dedicated DSD pins must be tied low while not in use.
7.2.2
Digital Interface Format (DIF2:0) BITs 6-4
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format, and the options are detailed in Figures 3 through 5.
DIF2
0
0
0
0
1
1
1
1
DIF1
0
0
1
1
0
0
1
1
DIF0
0
1
0
1
0
1
0
1
Description
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Reserved
Reserved
Table 5. Digital Interface Formats - PCM Mode
Format
0 (Default)
1
2
3
4
5
Figure
3
4
5
5
5
5
DS568F1
29
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