CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
CS43L22
SWITCHING SPECIFICATIONS - SERIAL PORT
Inputs: Logic 0 = DGND; Logic 1 = VL.
RESET pin Low Pulse Width
MCLK Frequency (Note 12)
Parameters
MCLK Duty Cycle
Slave Mode
Symbol
(Note 11)
Min
Max
1
-
(See “Serial Port Clock-
ing” on page 29)
45
55
Units
ms
MHz
%
Sample Rate (LRCK)
LRCK Duty Cycle
SCLK Frequency
SCLK Duty Cycle
LRCK Setup Time Before SCLK Rising Edge
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
Master Mode
Fs
(See “Serial Port Clock- kHz
ing” on page 29)
45
55
%
1/tP
-
64•Fs
Hz
45
55
%
ts(LK-SK)
40
ts(SD-SK)
20
th
20
-
ns
-
ns
-
ns
Sample Rate (LRCK)
Fs
(See “Serial Port Clock- Hz
ing” on page 29)
LRCK Duty Cycle
45
55
%
SCLK Frequency
SCLK Duty Cycle
SCLK=MCLK mode 1/tP
MCLK=12.0000 MHz 1/tP
all other modes 1/tP
-
12.0000 MHz
-
68•Fs
Hz
-
64•Fs
Hz
45
55
%
SDIN Setup Time Before SCLK Rising Edge
SDIN Hold Time After SCLK Rising Edge
ts(SD-SK)
20
th
20
-
ns
-
ns
11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are
settled.
12. See “Example System Clock Frequencies” on page 61 for typical MCLK frequencies.
LRCK
SCLK
ts(LK-SK)
//
//
tP
//
//
SDIN
ts(SD-SK)
th
//
MSB
//
MSB-1
Figure 3. Serial Audio Interface Timing
16
DS792F2
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