CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
SWITCHING SPECIFICATIONS - I²C CONTROL PORT
Inputs: Logic 0 = DGND; Logic 1 = V; SDA CL = 30 pF.
Parameters
Symbol
Min
SCL Clock Frequency
fscl
-
RESET Rising Edge to Start
tirs
550
Bus Free Time Between Transmissions
tbuf
4.7
Start Condition Hold Time (prior to first clock pulse)
thdst
4.0
Clock Low time
tlow
4.7
Clock High Time
thigh
4.0
Setup Time for Repeated Start Condition
tsust
4.7
SDA Hold Time from SCL Falling
(Note 13)
thdd
0
SDA Setup time to SCL Rising
tsud
250
Rise Time of SCL and SDA
trc
-
Fall Time SCL and SDA
tfc
-
Setup Time for Stop Condition
tsusp
4.7
Acknowledge Delay from SCL Falling
tack
300
13. Data must be held for sufficient time to bridge the transition time, tfc, of SCL.
Max
100
-
-
-
-
-
-
-
-
1
300
-
1000
CS43L22
Unit
kHz
ns
µs
µs
µs
µs
µs
µs
ns
µs
ns
µs
ns
RESET
t irs
Stop
Start
Repeated
Start
SDA
t buf
t hdst
t high
t hdst
tf
SCL
t low t hdd
t sud
t sust
tr
Figure 4. Control Port Timing - I²C
Stop
t susp
DS792F2
17
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