CS43L22 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS43L22

Low Power, Stereo DAC w/Headphone & Speaker Amps

Cirrus Logic 

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7.5.5

Confidential Draft

3/4/10

CS43L22

Audio Word Length

Configures the audio sample word length used for the data into SDIN.

AWL[1:0]

00

01

10

11

Application:

Audio Word Length

DSP Mode

32-bit data

24-bit data

20-bit data

16-bit data

“DSP Mode” on page 31

Right Justified

24-bit data

20-bit data

18-bit data

16-bit data

Note: When the internal MCLK/LRCK ratio is set to 125 in Master Mode, the 32-bit data width option

for DSP Mode is not valid unless SCLK=MCLK.

7.6 Interface Control 2 (Address 07h)

7

6

5

Reserved SCLK=MCLK Reserved

4

Reserved

3

INV_SWCH

2

Reserved

1

Reserved

0

Reserved

7.6.1

SCLK equals MCLK

Configures the SCLK signal source for Master Mode.

SCLK=MCLK

0

1

Output SCLK

Re-timed signal, synchronously derived from MCLK

Non-retimed, MCLK signal

Note: This bit is only valid for MCLK = 12.0000 MHz.

7.6.2

Speaker/Headphone Switch Invert

Determines the control signal polarity of the SPK/HP_SW pin.

INV_SWCH

0

1

SPK/HP_SW pin 6 Control

Not inverted

Inverted

DS792F2

41

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