CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
7.12.5 Speaker MONO Control
Configures a parallel full bridge output for the speaker channels.
SPKMONO
0
1
Application:
Parallel Full Bridge Output
Disabled
Enabled
“Mono Speaker Output Configuration” on page 27
CS43L22
7.12.6 Speaker Mute 50/50 Control
Configures how the speaker channels mute.
MUTE50/50
0
1
Speaker Mute 50/50
Disabled; The PWM amplifiers outputs modulated silence when SPKxMUTE is enabled.
Enabled; The PWM amplifiers switch at an exact 50%-duty-cycle signal (not modulated) when SPKxMUTE is
enabled.
7.13 Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h)
7
6
5
4
3
2
1
0
PASSxVOL7 PASSxVOL6 PASSxVOL5 PASSxVOL4 PASSxVOL3 PASSxVOL2 PASSxVOL1 PASSxVOL0
7.13.1 Passthrough x Volume
Sets the volume/gain of the analog input signal routed to the headphone/line output.
PASSxVOL[7:0]
0111 1111
...
0001 1000
...
0000 0001
0000 0000
11111 1111
...
1000 1000
...
1000 0000
Step Size:
Application:
Gain
12 dB
...
12 dB
...
+0.5 dB
0 dB
-0.5 dB
...
-60.0 dB
...
-60.0 dB
0.5 dB (approximate)
“Passthrough Analog” on page 44
Notes:
1. This register is ignored when the PASSTHRUx bit (“Passthrough Analog” on page 44) is disabled.
2. The step size may deviate from 0.5 dB at settings below -40 dB. Code settings 0x95, 0xA1, 0xAD and
0xB9 are not guaranteed to be monotonic.
46
DS792F2
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