CS43L22 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L22' PDF : 66 Pages View PDF
Confidential Draft
3/4/10
CS43L22
7.25 Limiter Attack Rate (Address 29h)
7
Reserved
6
Reserved
5
4
LIMARATE5 LIMARATE4
3
LIMARATE3
2
LIMARATE2
1
LIMARATE1
0
LIMARATE0
7.25.1 Limiter Attack Rate
Sets the rate at which the limiter applies digital attenuation from levels above the MAX[2:0] threshold
(“Limiter Maximum Threshold” on page 53).
LIMARATE[5:0]
00 0000
···
11 1111
Application:
Attack Time
Fastest Attack
···
Slowest Attack
“Limiter” on page 22
Note: The limiter attack rate is user-selectable but is also a function of the sampling frequency, Fs, and
the DIGSFT (“Digital Soft Ramp” on page 44) and DIGZC (“Digital Zero Cross” on page 45) setting unless
the respective disable bit (“Limiter Soft Ramp Disable” on page 53 or “Limiter Zero Cross Disable” on
page 54) is enabled.
7.26 Status (Address 2Eh) (Read Only)
For all bits in this register, a “1” means the associated error condition has occurred at least once since the
register was last read. A”0” means the associated error condition has NOT occurred since the last reading
of the register. Reading the register resets all bits to 0.
7
Reserved
6
5
4
3
2
SPCLKERR DSPAOVFL DSPBOVFL PCMAOVFL PCMBOVFL
1
Reserved
0
Reserved
7.26.1 Serial Port Clock Error (Read Only)
Indicates the status of the MCLK to LRCK ratio.
SPCLKERR
0
1
Application:
Serial Port Clock Status:
MCLK/LRCK ratio is valid.
MCLK/LRCK ratio is not valid.
“Serial Port Clocking” on page 29
Note: On initial power up and application of clocks, this bit will report ‘1’b as the serial port re-synchro-
nizes.
7.26.2 DSP Engine Overflow (Read Only)
Indicates the over-range status in the DSP data path.
DSPxOVFL
0
1
Application:
DSP Overflow Status:
No digital clipping has occurred in the data path after the DSP.
Digital clipping has occurred in the data path after the DSP.
“DSP Engine” on page 21
DS792F2
55
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