CS43L43 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS43L43' PDF : 36 Pages View PDF
CS43L43
SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE (Inputs: Logic “0” =
GND, Logic “1” = VL.)
External SCLK Mode
MCLK Frequency
MCLK Duty Cycle
Input Sample Rate
Parameters
LRCK Duty Cycle
SCLK Pulse Width Low
SCLK Pulse Width High
SCLK Period
SCLK Frequency
SCLK Frequency
SCLK rising to LRCK edge delay
SCLK rising to LRCK edge setup time
SDATA valid to SCLK rising setup time
SCLK rising to SDATA hold time
Symbol
Min
Max Units
Single-Speed Mode Fs
Double-Speed Mode Fs
tsclkl
tsclkh
tsclkw
(Note 10)
tslrd
tslrs
tsdlrs
tsdh
1.024
45
2
50
40
20
20
--------2----------
MCLK
-
-
20
20
20
20
51.2
55
50
100
60
-
-
-
M------C-----L----K---
2
M------C-----L----K---
4
-
-
-
-
MHz
%
kHz
kHz
%
ns
ns
s
Hz
Hz
ns
ns
ns
ns
Notes: 5. This serial clock is required only in Control Port Mode when the MCLK Divide bit is enabled.
LRCK
t slrd
t slrs
t sclkh
t sclkl
SCLK
t sdlrs
t sdh
SDATA
Figure 19. External Se- rial Mode Input Timing
30
DS479PP3
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