CS5166GDWR16 View Datasheet(PDF) - ON Semiconductor
Part Name
Description
MFG CO.
'CS5166GDWR16' PDF : 25 Pages View PDF
CS5166
5.0 V
MMUN2111T1 (SOT−23)
Shutdown
Input
IN4148
5
SS
CS5166
8
ISENSE
Figure 27. Implementing Shutdown with the CS5166
Selecting External Components
The CS5166 buck regulator can be used with a wide range
of external power components to optimize the cost and
performance of a particular design. The following
information can be used as general guidelines to assist in
their selection.
NFET Power Transistors
Both logic level and standard FETs can be used. The
reference designs derive gate drive from the 12 V supply
which is generally available in most computer systems and
utilize logic level FETs. A charge pump may be easily
implemented to support 5.0 V only systems. Multiple
FET’s may be paralleled to reduce losses and improve
efficiency and thermal management.
Voltage applied to the FET gates depends on the
application circuit used. Both upper and lower gate driver
outputs are specified to drive to within 1.5 V of ground when
in the low state and to within 2.0 V of their respective bias
supplies when in the high state. In practice, the FET gates
will be driven rail to rail due to overshoot caused by the
capacitive load they present to the controller IC. For the
typical application where VCC = 12 V and 5.0 V is used as
the source for the regulator output current, the following
gate drive is provided:
VGS(TOP) + 12 V * 5.0 V + 7.0 V
VGS(BOTTOM) + 12 V
(see Figure 28)
Trace 3− GATE(H) (10 V/div.)
Trace 1− GATE(H) − 5.0 VIN
Trace 4− GATE(L) (10 V/div.)
Trace 2− Inductor Switching Node (5.0 V/div.)
Figure 28. Gate Drive Waveforms Depicting
Rail to Rail Swing
Trace 1 = GATE(H) (5.0 V/div.)
Trace 2 = GATE(L) (5.0 V/div.)
Figure 29. Normal Operation Showing the Guaranteed
Non−Overlap Time Between the High and Low−Side
MOSFET Gate Drives, ILOAD = 14 A
The CS5166 provides adaptive control of the external
NFET conduction times by guaranteeing a typical 65 ns
non−overlap (as seen in Figure 29) between the upper and
lower MOSFET gate drive pulses. This feature eliminates
the potentially catastrophic effect of “shoot−through
current”, a condition during which both FETs conduct
causing them to overheat, self−destruct, and possibly inflict
irreversible damage to the processor.
The most important aspect of FET performance is
RDSON, which effects regulator efficiency and FET thermal
management requirements.
The power dissipated by the MOSFETs may be estimated
as follows:
Switching MOSFET:
Power + ILOAD2 RDSON duty cycle
Synchronous MOSFET:
Power + ILOAD2 RDSON (1 * duty cycle)
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