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CS5166GDWR16 View Datasheet(PDF) - ON Semiconductor

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MFG CO.
'CS5166GDWR16' PDF : 25 Pages View PDF
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CS5166
Implementing Current Sharing Using the “Droop
Resistor”
In addition to improving load transient performance, the
CS5166 V2 control method allows the droop resistor to
provide the additional capability to easily implement current
sharing. Figure 31 shows a simplified schematic of two
current sharing synchronous buck regulators. Each buck
regulator’s droop resistor is terminated at the load. The
PWM control signal from each Error Amp is connected
together, causing the inner PWM loop to regulate to a
common voltage. Since the voltage at each resistor terminal
is the same, this configuration results in equal voltage being
applied across each matched droop resistor. The result is
equal current flowing through each buck regulator. An
additional benefit is that synchronization to a common
switching frequency tends to be achieved because each
regulator shares a common PWM ramp signal.
In practice, each buck regulator will regulate to a slightly
different output voltage due to mismatching of the PWM
comparators, slope of the PWM ramp (output voltage
ripple), and propagation delays. At light loads, the results
can be very poor current sharing. With zero output current,
some regulators may be sourcing current while others may
be sinking current.
This results in additional power dissipation and lower
efficiency than would be obtained by a single regulator. This
is usually not an issue since efficiency is most important
when a supply is fully loaded.
This effect is similar to the difference in efficiency
between synchronous and nonsynchronous buck
regulators. Synchronous buck regulators have lower
efficiency at light loads because inductor current is always
continuous, flowing from the load to ground during switch
offtime through the synchronous rectifier. Under full load
conditions, the synchronous design is more efficient due to
the lower voltage drop across the synchronous rectifier.
Likewise, the efficiency of droop sharing regulators will be
lower at light loads due to the continuous current flow in the
droop resistors. Efficiency at heavy loads tends to be higher
due to reduced I2R losses.
The output current of each regulator can be calculated
from:
IN
+
(VOUT(N) * VOUT)
RDROOP(N)
where: VOUT(N) and RDROOP(N) are the output voltage
and droop resistance of a particular regulator and VOUT is
the system output voltage. Output current is the sum of each
regulator’s current:
IOUT + I1 ) I2 ) AAA ) IN
Current sharing improves with increasing load current.
The increasing voltage drop across the droop resistor due to
increasing load current eventually swamps out the
differences in regulator output voltages. If a large enough
voltage can be developed across the droop resistors, current
sharing accuracy will be determined solely by their
matching. To realize the benefits of current sharing, it is not
necessary to obtain perfect matching. Keeping output
currents within ± 10% is usually acceptable.
For microprocessor applications, the value of the droop
resistor must be selected to optimize adaptive voltage
positioning, current sharing, current limit and efficiency.
Current sharing is realized by simply connecting the COMP
pins of the respective buck regulators, as shown in Figure 31.
Figure 32 shows operation with no load. In this case, there
is insufficient output voltage ripple across the droop resistor
to produce complete synchronization. Duty Cycle is close to
the theoretical 56% (VOUT/VIN) resulting in a switching
frequency of approximately 275 kHz.
Figure 34 shows operation with a 30 Amp load.
Synchronization between the two regulators is now obtained
due to increased ripple voltage. Increases losses cause the V2
control loop to increase ontime to compensate. This results
in a larger duty cycle and a corresponding decrease in
switching frequency to 233 kHz.
Trace 1 = Output voltage ripple.
Trace 2 = Buck regulator #1 inductor switching node.
Trace 3 = Buck regulator #2 inductor switching node.
Figure 32. No Load Waveforms
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