CS5373A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS5373A' PDF : 40 Pages View PDF
CS5373A
mance specifications than the BUF± outputs,
but with a much higher sensitivity to external
loading. Excessive resistive or capacitive load-
ing on the OUT± pins will degrade the analog
performance characteristics of the test DAC in
all operational modes.
The OUT± precision output is optimized for di-
rect connection to the CS3301A / CS3302A
amplifier differential inputs, which have very
high input impedance. These amplifiers in-
clude a pin-controlled input multiplexer to
switch between an internal differential termina-
tion for noise tests and two external differential
inputs. One external input is typically dedicat-
ed to sensor measurements and the other to
testing the electronics channel.
The OUT± outputs are enabled in all opera-
tional modes except modulator mode
(MODE 0), “AC BUF Only” mode (MODE 3)
and sleep mode (MODE 7). In these modes
the OUT± pins are high impedance.
7.4 DAC BUF± Buffered Output
The test DAC BUF± pins are buffered differen-
tial analog outputs for testing external sensors
such as geophones or hydrophones. The buff-
ered outputs have reduced performance spec-
ifications compared with the OUT± outputs,
but are less sensitive to external loading.
The BUF± outputs are enabled in all operation-
al modes except modulator mode (MODE 0),
“AC OUT Only” mode (MODE 2) and sleep
mode (MODE 7). In these modes the BUF±
pins are high impedance to ensure they do not
interfere with sensor operation during normal
data acquisition.
For sensor impedance testing, it is required to
place matched series resistors in between the
BUF± outputs and the differential sensor. With
known series resistors and a known DC differ-
ential source voltage, sensor resistance can
be calculated ratiometrically from the mea-
sured voltage drop across the sensor.
7.5 DAC CAP± Connection
The CS5373A test DAC requires a 10 nF C0G
type capacitor to be connected differentially
across the CAP± pins. This capacitor creates
an internal anti-alias filter to eliminate high-fre-
quency signals from the OUT± and BUF± ana-
log outputs and helps to maintain the stability
of the low-power ∆Σ DAC circuitry.
A COG, NPO or similar high-quality capacitor
is required for CAP± since other capacitor
types, such as X7R, do not have the required
linearity. Using a poor-quality capacitor on
CAP± will significantly degrade THD perfor-
mance of the test DAC AC operational modes.
7.6 Analog Differential Signals
Differential AC test signals into and out of the
CS5373A consist of two halves with equal but
opposite magnitude varying about a common
mode voltage. A full-scale 5 VPP differential
AC signal centered on a -0.15 V common
mode voltage will have:
SIG+ = -0.15 V + 1.25 V = +1.1 V
SIG- = -0.15 V - 1.25 V = -1.4 V
SIG+ is +2.5 V relative to SIG-
For the opposite case:
SIG+ = -0.15 V - 1.25 V = -1.4 V
SIG- = -0.15 V + 1.25 V = +1.1 V
SIG+ is -2.5 V relative to SIG-
So the total swing for SIG+ relative to SIG- is
(+2.5 V) - (-2.5 V) = 5 Vpp differential. A similar
calculation can be done for SIG- relative to
SIG+. It’s important to note that a 5 Vpp differ-
ential signal centered on a -0.15 V common
mode voltage never exceeds +1.1 V with re-
spect to ground and never drops below -1.4 V
with respect to ground on either half. By defini-
tion, differential voltages are measured with
respect to the opposite half, not relative to
ground. A voltmeter differentially measuring
between SIG+ and SIG- in the above example
would correctly read 1.767 Vrms, or 5 Vpp.
30
DS703F1
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