CS8900-CQ3 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8900-CQ3' PDF : 138 Pages View PDF
CS8900A
Crystal LAN™ ISA Ethernet Controller
information should be obtained from the DMA
buffer.
5.4.5 Committing Buffer Space to a DMAed
Frame
Although a receive frame may occupy space in the
host memory’s circular DMA buffer, the
CS8900A’s Memory Manager does not commit the
buffer space to the receive frame until the entire
frame has been transferred and the host learns of
the frame’s existence by reading the Frame Count
register (PacketPage base + 0028h).
When the CS8900A commits DMA buffer space to
a particular DMAed receive frame (termed a com-
mitted received frame), no data from subsequent
frames can be written to that buffer space until the
committed received frame is freed from commit-
ment. (The committed received frame may or may
not have been received error free.)
A committed DMAed receive frame is freed from
commitment by any one of the following condi-
tions:
1) The host rereads the DMA Frame Count regis-
ter (PacketPage base + 0028h).
2) New frames have been transferred via DMA,
and the host reads the BufEvent register (either
directly or from the ISQ) and sees that the RxD-
MAFrame bit is set (this condition is termed an
"implied Skip").
3) The host issues a Reset-DMA command by set-
ting the ResetRxDMA bit (Register 17, Bus-
CTL, Bit 6).
5.4.6 DMA Buffer Organization
When DMA is used to transfer receive frames, the
DMA Start-of-Frame register (PacketPage Base +
0026h) defines the offset from the DMA base to the
start of the most recently transferred received
frame. Frames stored in the DMA buffer are trans-
ferred as words and maintain double-word (32-bit)
alignment. Unfilled memory space between suc-
cessive frames stored in the DMA buffer may result
from double-word alignment. These "holes" may
be 1, 2, or 3 bytes, depending on the length of the
frame preceding the hole.
5.4.7 RxDMAFrame Bit
The RxDMAFrame bit (Register C, BufEvent, bit
7) is controlled by the CS8900A and is set whenev-
er the value in the DMA Frame Count register is
non-zero. The host cannot clear RxDMAFrame by
reading the BufEvent register (Register C).
Table 27 summarizes the criteria used to set and
clear RxDMAFrame.
Non-Stream
Transfer Mode
Stream Transfer
Mode (see
Section 5.6)
To set RxD- The RxDMAFrame The RxDMAFrame
MAFrame bit is set whenever bit is set at the end
the DMA Frame of a Stream Transfer
Count register
cycle.
(PacketPage base +
0028h) transitions to
non-zero.
To Clear
RxDMA-
Frame
The DMA Frame
Count is zero.
The DMA Frame
Count is zero.
Table 27. RxDMAFrame Bit
5.4.8 Receive DMA Example Without Wrap-
Around
Figure 24 shows three frames stored in host mem-
ory by DMA without wrap-around.
5.4.9 Receive DMA Operation for RxDMA-Only
Mode
In an RxDMAOnly mode, a system DMA moves
all the received frames from the on-chip memory to
an external 16- or 64-Kbyte buffer memory. The
received frame must have passed the destination
address filter, and must be completely received.
Usually, the DMA receive frame interrupt (RxD-
MAiE, bit 7, Register B, BufCFG) is set so that the
CS8900A generates an interrupt when a frame is
transferred by DMA. Figure 25 shows how a DMA
Receive Frame interrupt is processed.
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