CS8900-IQ3 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8900-IQ3' PDF : 138 Pages View PDF
CS8900A
Crystal LAN™ ISA Ethernet Controller
1.6 µs after the end of transmission. During this pe-
riod, the CS8900A ignores receive carrier activity
(see SQE Error in this section for more informa-
tion).
3.10 Encoder/Decoder (ENDEC)
The CS8900A’s integrated encoder/decoder (EN-
DEC) circuit is compliant with the relevant por-
tions of section 7 of the Ethernet standard (ISO/IEC
8802-3, 1993). Its primary functions include:
Manchester encoding of transmit data; informing
the MAC when valid receive data is present (Carri-
er Detection); and, recovering the clock and NRZ
data from incoming Manchester-encoded data.
Figure 12 provides a block diagram of the ENDEC
and how it interfaces to the MAC, AUI and
10BASE-T transceiver.
3.10.1 Encoder
The encoder converts NRZ data from the MAC and
a 20 MHz Transmit Clock signal into a serial
stream of Manchester data. The Transmit Clock is
produced by an on-chip oscillator circuit that is
driven by either an external 20 MHz quartz crystal
or a TTL-level CMOS clock input. If a CMOS in-
put is used, the clock should be 20 MHz ±0.01%
with a duty cycle between 40% and 60%. The spec-
ifications for the crystal are described in
Section 7.7 on page 120. The encoded signal is
routed to either the 10BASE-T transceiver or AUI,
depending on configuration.
3.10.2 Carrier Detection
The internal Carrier Detection circuit informs the
MAC that valid receive data is present by asserting
the internal Carrier Sense signal as soon it detects a
valid bit pattern (1010b or 0101b for 10BASE-T,
and 1b or 0b for AUI). During normal packet recep-
tion, Carrier Sense remains asserted while the
frame is being received, and is deasserted 1.3 to 2.3
bit times after the last low-to-high transition of the
End-of-Frame (EOF) sequence. Whenever the re-
ceiver is idle (no receive activity), Carrier Sense is
deasserted. The CRS bit (Register 14, LineST,
Bit E) reports the state of the Carrier Sense signal.
3.10.3 Clock and Data Recovery
When the receiver is idle, the phase-lock loop
(PLL) is locked to the internal clock signal. The as-
sertion of the Carrier Sense signal interrupts the
PLL. When it restarts, it locks on the incoming da-
ta. The receive clock is then compared to the in-
coming data at the bit cell center and any phase
difference is corrected. The PLL remains locked as
long as the receiver input signal is valid. Once the
PLL has locked on the incoming data, the ENDEC
converts the Manchester data to NRZ and passes
the decoded data and the recovered clock to the
MAC for further processing.
Carrier Sense
RX CLK
MAC
RX NRZ
TXCLK
TX NRZ
TEN
Port Select
Collision
ENDEC
Carrier
Detector
Decoder
& PLL
RX
MUX
Encoder
TX
MUX
RXSQL
10BASE-T
RX
Transceiver
TX
AUISQL
AUIRX
AUITX
AUI
AUICol
Clock
Figure 12. ENDEC
CIRRUS LOGIC PRODUCT DATASHEET
DS271PP4
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