CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
• all packets received are of legal length with
valid CRC;
• each packet follows its predecessor by less
than 52 µs; and,
• the DA of each packet passes the DA filter.
Example of StreamTransfer
Figure 5.10 shows how four back-to-back
frames, followed by five back-to-back frames,
would be received without StreamTransfer. Fig-
ure 5.11 shows how the same sequence of frames
would be received with StreamTransfer.
If any of these conditions are not met, the
CS8920A exits StreamTransfer by generating
RxOK and RxDMA interrupts. The CS8920A
then returns to either Memory, I/O, or DMA
mode, depending on configuration.
Receive DMA Summary
Table 5.11 summarizes the Receive DMA con-
figuration options supported by the CS8920A.
4 Back-to-Back Frames
T > 52 us
5 Back-to-Back Frames
Interrupt
Request
9 Interrupts for 9 "Good" Packets
Time
Figure 5.10. Receive Example Without Stream Transfer
4 Back-to-Back Frames
T > 52 us
5 Back-to-Back Frames
Interrupt
Request
2 Interrupts for 9 "Good" Packets
Time
Figure 5.11. Receive Example With Stream Transfer
RxDMAonly
(Register 3,
RxCFG, Bit 9)
1
1
0
0
0
AutoRxDMAiE
(Register 3,
RxCFG, Bit A)
NA
RxDMAiE
(Register B,
BufCFG, Bit 7)
0
NA
1
1
0
1
1
0
NA
RxOKiE
(Register 3,
RxCFG, Bit 8)
0
0
0
1
1
CS8920A Configuration
Receive DMA used for all receive frames,
without interrupts.
Receive DMA used for all receive frames, with
BufEvent interrupts.
Auto-Switch DMA used if necessary, without
interrupts.
Auto-Switch DMA used if necessary, with
RxEvent and BufEvent interrupts possible.
Memory or I/O Mode only.
Table 5.11. Receive DMA Configuration Options
DS238PP2
107
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