CS8920A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS8920A' PDF : 144 Pages View PDF
The CS8920A does not support connection to 8-
bit buses.
To transfer transmit frames to the CS8920A and
receive frames from the CS8920A, the host may
mix word and byte transfers, provided it follows
three rules:
1.The primary method used to access CS8920A
memory is word access.
2.Word accesses to the CS8920A’s internal mem-
ory are kept on even-byte boundaries.
3.When switching from byte accesses to word
accesses, a byte access to an even byte address
must be followed by a byte access to an odd-
byte address before the host may execute a
word access (this will re-align the word trans-
fers to even-byte boundaries). On the other
hand, a byte access to an odd-byte address
may be followed by a word access.
Failure to observe these three rules may cause
data corruption.
Transferring Odd-Byte-Aligned Data
Some applications gather transmit data from
more than one section of host memory. The
boundary between the various memory locations
may be either even- or odd-byte aligned. When
such a boundary is odd-byte aligned, the host
should transfer the last byte of the first block to
an even address, followed by the first byte of the
second block to the following odd address. It can
then resume word transfers. An example of this
is shown in Figure 4.3.
Random Access to CS8920A Memory
The first 118 bytes of a receive frame held in the
CS8920A’s on-chip memory may be randomly
accessed in Memory mode. After the first 118
bytes, only sequential access of received data is
allowed. Either byte or word access is permitted,
DS238PP2
Word Transfer
CS8920A
Word Transfer
Word Transfer
Byte Transfer
Byte Transfer
Word Transfer
Word Transfer
First Block of Data
Second Block of Data
Word Transfer
Figure 4.3. Odd-Byte Aligned Data
as long as all word accesses are executed to
even-byte boundaries.
4.11 Memory Mode Operation
To configure the CS8920A for Memory Mode,
the PacketPage memory must be mapped into a
contiguous 4-Kbyte block of host memory. The
block must start at an X000h boundary, with the
PacketPage base address mapped to X000h.
When the CS8920A comes out of reset, its de-
fault configuration is I/O Mode. When Memory
Mode is selected, all of the CS8920A’s registers
can be accessed directly.
In Memory Mode, the CS8920A supports Stand-
ard or Ready Bus cycles without introducing
additional wait states (i.e., IOCHRDY is not
deasserted).
Memory moves can use MOVD (double-word
transfers) as long as the CS8920A’s memory
base address is on a double word boundary. Be-
cause 286 processors don’t support the MOVD
instruction, word and byte transfers must be used
with a 286.
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