CS8920A View Datasheet(PDF) - Cirrus Logic
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MFG CO.
'CS8920A' PDF : 144 Pages View PDF
CS8920A
5.0 OPERATION
5.1 Managing Interrupts and Servicing
the Interrupt Status Queue
The Interrupt Status Queue (ISQ) is used by the
CS8920A to communicate Event reports to the
host processor. Whenever an event occurs that
triggers an enabled interrupt, the CS8920A sets
the appropriate bit(s) in one of five registers,
maps the contents of that register to the ISQ, and
drives the selected interrupt request pin high (if
an earlier interrupt is waiting in the queue, the
interrupt request pin will already be high). When
the host services the interrupt, it must first read
the ISQ to learn the nature of the interrupt. It can
then process the interrupt (the first read to the
ISQ causes the interrupt request pin to go low.
Three of the registers mapped to the ISQ are
event registers: RxEvent (Register 4), TxEvent
(Register 8), and BufEvent (Register C). The
other two registers are counter-overflow reports:
RxMISS (Register 10) and TxCOL (Register 12).
There may be more than one RxEvent report
and/or more than one TxEvent report in the ISQ
at a time. However, there may be only one
BufEvent report, one RxMISS report and one
TxCOL report in the ISQ at a time.
Event reports stored in the ISQ are read out in
the order of priority, with RxEvent first, followed
by TxEvent, BufEvent, RxMiss, and then
TxCOL. The host only needs to read from one
location to get the interrupt currently at the front
of the queue. In Memory Mode, the ISQ is lo-
cated at PacketPage base + 0120h. In I/O Mode,
it is located at I/O base + 0008h. Each time the
host reads the ISQ, the bits in the corresponding
register are cleared and the next report in the
queue moves to the front.
When the host starts reading the ISQ, it must
read and process all Event reports in the queue.
A readout of a null word (0000h) indicates that
all interrupts have been read.
The ISQ is read as a 16-bit word. The lower six
bits (0 through 5) contain the register number (4,
8, C, 10, or 12). The upper ten bits (6 through F)
contain the register contents. The host must al-
ways read the entire 16-bit word, because the
CS8920A does not support 8-bit access to its in-
ternal registers. Figure 5.1 shows the operation
of the ISQ.
The active interrupt pin (INTRQx) is selected via
the Interrupt Number register (PacketPage base +
0370h). As an additional option, all of the inter-
rupt pins can be placed in the high-impedance
state using the same register. See Section 4.3.
An event triggers an interrupt only when the En-
ableIRQ bit of the Bus Control register (bit F of
register 17) is set.
After the CS8920A has generated an interrupt,
the first read of the ISQ makes the INTRQ out-
put pin go low (inactive). INTRQ remains low
until the null word (0000h) is read from the ISQ,
or for 1.6 µs, whichever is longer.
Typically, when interrupts have been enabled for
various error conditions (runt, CRC error, frame
> 1518 bytes) via register 3, the software will
also select that those frames be discarded (regis-
ter 5).
86
DS238PP2
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