CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
data and is cleared when it no longer contains any valid data. This bit can be polled when using pro-
grammed I/O to remove remaining data from the receive FIFO. This bit does not request an interrupt.
3.16.6.13 FIFO Operation Completed Flag (FIFO)
The FIFO Operation Completed (FIFO) Flag is set after the FIFO operation requested by writing to
DAIDR2 as completed.
FIFO is automatically cleared when DAIDR2 is read or written. This bit does not request an interrupt.
3.16.7 DAI64Fs Control (address 0x8000.2600)
The DAI now includes a divider network for the frequency of the clock source. The CS89712 provides
for both 128 and 64 times the sample frequency (128 fs and 64 fs) to better support the various MP3
sample rates. There are two clocks to choose from: 73.728 MHz PLL clock as well as the 11.2896
Mhz external clock. The purpose is support more devices that use the 64 fs rate. Both clocks are fixed
rate clocks so the divider network (AUDIV) is required.
31-15 14-8
7-6
5
4
3
2
1
0
AUDDIV
LOOPBACK
MCLK256EN AUDCLKSRC AUDIOCLKEN I2SFS64
Bit
0
1
2
3
4
5
6-7
8-14
15-31
Description
I2SF64: 0 => 128 fs 1=>64 fs If high, SYSCON3 bit 9 must be low. The converse is also true.
AUDCLKEN: Enable audio clock generator
AUDCLKSRC: ClockSource 0=>73.728MHz(PLL) 1=>11.2896MHz(ExtClock)
MCLK256EN: Selects MCLK (256 fs) or the BUZZ pin
Reserved
LOOPBACK: Test mode. Digital data normally output to DAC loops internally.
Reserved
AUDIV: Frequency divisor for sample frequency and bit clock using either the external clock or
the PLL clock for the audio clock generator
Reserved
Table 63. DAI64Fs Control Register
Clock
Source (MHz)
73.728
11.2896
73.728
11.2896
73.728
73.728
11.2896
73.728
Sample
Frequency (KHz)
8
11.025
16
22.050
24
32
44.1
48
128 fs
Audio Bit
Clock (MHz)
1.0240
1.4112
1.5360
2.8224
3.0720
4.0960
5.6448
6.1440
64 fs
Audio Bit Clock
(MHz)
0.5120
0.7056
0.7680
1.4112
1.5360
2.0480
2.8224
3.0720
Table 64. Clock Source for 64 fs and 128 fs
128 fs
Divisor
(AUDDIV)
36
8
18
4
12
9
2
6
64 fs
Divisor
(AUDDIV)
72
16
36
8
24
18
4
12
DS502PP2
115
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