CS89712 View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
'CS89712' PDF : 170 Pages View PDF
CS89712
3.17 Ethernet Bus Interface Registers
3.17.1 Master Interrupt Enable (address offset 0022h)
Address 0023h
00h
Reset value is: XXXX XXXX XXXX X100 - Interrupts disabled
Address 0022h
Interrupt number assignment:
0000 0000b = Enable
0000 01xxb = Disable
3.17.2 EEPROM Command (address offset 0040h)
7:0
ADD7 to ADD0
F:B
Reserved
A
Reserved
9
OB1
8
OB0
This register is used to control the reading, writing and erasing of the EEPROM. See Section 2.24, “Programming
the EEPROM”.
Bit
7:0
9:8
A
F:B
Description
ADD7-ADD0: Address of the EEPROM word being accessed.
OB1,OB0: Indicates the Opcode of the command being executed. See Table 26.
Reserved: Reserved and must be written as 0.
Reserved: Reserved and must be written as 0.
Table 65. EEPROM Command Bits
Reset value is: XXXX XXXX XXXX XXXX
3.17.3 EEPROM Data (address offset 0042h)
Address 0043h
Most significant byte of the EEPROM data.
Address 0042h
Least significant byte of the EEPROM data.
This register contains the word being written to, or read from, the EEPROM. See Section 2.24, “Programming the
EEPROM”.
Reset value is: XXXX XXXX XXXX XXXX
3.17.4 Receive Frame Byte Counter (address offset 0050h)
Address 0051h
Most significant byte of the byte count.
Address 0050h
Least significant byte of the byte count.
This register contains the count of the total number bytes received in the current received frame. This count contin-
uously increments as more bytes in this frame are received. See Section 2.32, “Basic Receive Operation”.
Reset value is: XXXX XXXX XXXX XXXX
3.18 Ethernet Port Status/Control Registers
3.18.1 Interrupt Status Queue Register (ISQ, address 120h)
7:6
RegContent
5:0
RegNum
F:8
RegContent
The Interrupt Status Queue Register is used to provide interrupt information. Whenever an event occurs that triggers
an enabled interrupt, the Ethernet Port sets the appropriate bit(s) in one of five registers, maps the contents of that
register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers:
116
DS502PP2
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