CSR8615 View Datasheet(PDF) - Unspecified
Part Name
Description
MFG CO.
'CSR8615' PDF : 114 Pages View PDF
3 Clock Generation
CSR8615 QFN accepts a reference clock input from either a crystal or an external clock source, e.g. a TCXO.
The external reference clock is required in active and deep sleep modes and must be present when CSR8615 QFN
is enabled.
3.1 Crystal
CSR8615 QFN contains a crystal driver circuit that acts as a transconductance amplifier that drives an external
13 crystal connected between XTAL_IN and XTAL_OUT. The crystal driver circuit forms a Pierce oscillator with the
20 external crystal. External capacitors are not required for standard crystals that require a load capacitance of around
6, 9pF. CSR recommends this option.
er 1 gm
mb On-chip Capacitance Control
ay, Septe Amplifier gm
nd Control LVL[3:0]
ecomm.com.cn - Mo XTAL_IN
XTAL_OUT
Tsao - apach External Crystal
mes Figure 3.1: Crystal Oscillator Overview
for ja The on-chip capacitance is adjusted using PSKEY_XTAL_OSC_CONFIG, see Table 3.1. The default values suit a
d typical crystal requiring a 9pF load capacitance. In deep sleep mode, the crystal oscillation is maintained, but at a
re lower drive strength to reduce power consumption. The drive strength and load capacitance are configured with a
Prepa PS Key.
Normal Mode
Low Power Mode
PSKEY_XTAL_OSC_CONFIG [3:2]
PSKEY_XTAL_OSC_CONFIG [1:0]
Value
00
01
10
11
00
01
10
11
XTAL_IN
(Typical)
15.6 pF 10.8 pF 6.0 pF
1.1 pF
15.6 pF 10.8 pF 6.0 pF
1.1 pF
XTAL_OUT 20.8 pF
(Typical)
16.0 pF
11.2 pF
6.4 pF
16.0 pF 11.2 pF 6.4 pF
1.5 pF
Table 3.1: Typical On-chip Capacitance Values
Pre-production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
Page 25 of 114
CS-303726-DSP3
www.csr.com
Share Link: 
