CSR8615A04-IQQF-R View Datasheet(PDF) - Unspecified
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MFG CO.
'CSR8615A04-IQQF-R' PDF : 114 Pages View PDF
5 Kalimba DSP
The Kalimba DSP is an open platform DSP enabling signal processing functions to be performed on over‑air data
or codec data to enhance audio applications. Figure 5.1 shows the Kalimba DSP interfaces to other functional blocks
within CSR8615 QFN.
Kalimba DSP Core
2013 Memory
, Management
y, September 16 Unit
MCU Register Interface (including Debug)
DSP MMU Port
DSP, MCU and Memory Window Control
Programmable Clock = 80MHz
.cn - Monda DSP RAMs
om DM2
omm.c DM1
pachec PM
DSP Data Memory 2 Interface (DM2)
DSP Data Memory 1 Interface (DM1)
DSP Program Memory Interface (PM)
Data Memory
Inteface
Address
Generators
Instruction Decode
ALU
Program Flow
DEBUG
Clock Select
PIO
Internal Control Register
MMU Interface
Interrupt Controller
Timer
MCU Window
Flash Window
PIO In/Out
IRQ to Subsystem
IRQ from Subsystem
1µs Timer Clock
s Tsao - a Figure 5.1: Kalimba DSP Interface to Internal Functions
jame The key features of the DSP include:
for ■80MIPS performance, 24‑bit fixed point DSP core
ed ■Single‑cycle MAC; 24 x 24‑bit multiply and 56‑bit accumulate includes 2 rMAC registers and new
ar instructions for improved performance over previous architecture
rep ■32‑bit instruction word
P â– Separate program memory and dual data memory, enabling an ALU operation and up to 2 memory
accesses in a single cycle
■Zero overhead looping, including a very low‑power 32‑instruction cache
â– Zero overhead circular buffer indexing
■Single cycle barrel shifter with up to 56‑bit input and 56‑bit output
â– Multiple cycle divide (performed in the background)
â– Bit reversed addressing
â– Orthogonal instruction set
â– Low overhead interrupt
For more information see Kalimba Architecture 3 DSP User Guide.
Pre-production Information
© Cambridge Silicon Radio Limited 2013
Confidential Information - This Material is Subject to CSR's Non-disclosure Agreement
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