CXP852P32A View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
MFG CO.
'CXP852P32A' PDF : 21 Pages View PDF
CXP852P32A
(6) I2C bus timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pins
Conditions Min.
Max. Unit
SCL clock frequency
fSLC
SCL
0
100 kHz
Bus free time prior to transfer start
tBUF
SDA, SCL
4.7
µs
Transfer start hold time
tHD; STA
SDA, SCL
4.0
µs
Clock Low level width
tLOW
SCL
4.7
µs
Clock High level width
tHIGH
SCL
4.0
µs
Setup time during repetitive transfer
tSU; STA
SDA, SCL
4.7
µs
Data hold time
tHD; DAT
SDA, SCL
0∗1
µs
Data setup time
tSU; DAT
SDA, SCL
250
ns
SDA, SCL rise time
tR
SDA, SCL
1
µs
SDA, SCL fall time
tF
SDA, SCL
300 ns
Transfer end setup time
tSU; STO
SDA, SCL
4.7
µs
∗1 The data hold time does not take into consideration SCL rise time (300ns max.). Ensure that the data hold
time exceeds 300ns.
SDA
SCL
tBUF
tR
tHD; STA
P
S
tLOW
tF
tHD; DAT
tHIGH
tSU; DAT
Fig. 9. I2C bus transfer timing
tHD; STA
tSU; STA
St
tSU; STO
P
I2C device I2C device
RS
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
Fig. 10. Recommended circuit example for I2C device
• Pull-up resistors must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω and under) of SDA0 (or SDA1) and SCL0 (or SCL1) reduces spike noise
caused by CRT flashover.
– 17 –
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