CXP852P32A
(7) OSD (On-Screen Display) timing
(Ta = –10 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins Condition Min. Max. Unit
OSD clock frequency
HSYNC pulse width
HSYNC after-edge
rise time/fall time
VSYNC after-edge
rise time/fall time
fOSC
EXLC
XLC
Fig. 12
4
tHWD HSYNC Fig. 11 1.2
tHCG HSYNC Fig. 11
tVCG VSYNC Fig. 11
13
MHz
µs
200
ns
1.0
µs
HSYNC
when Bit 5 of OPOL register
(01FBH) is set to "0"
tHWD
tHCG
0.8VDD
0.2VDD
VSYNC
when Bit 4 of OPOL register
(01FBH) is set to "0"
tVCG
0.8VDD
0.2VDD
Fig. 11. OSC timing
EXLC
XLC
L
C1
C2
Fig. 12. LC oscillation circuit example
– 18 –