CY7C0241-25AXC View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C0241-25AXC

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

Cypress Semiconductor 

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CY7C024/024A/0241

CY7C025/0251

Switching Waveforms (continued)

Figure 9. Semaphore Read After Write Timing, Either Side[37]

A 0–A 2

VALID ADRESS

tAA

VALID ADRESS

tOHA

SEM

tAW

tHA

tSCE

tSOP

tACE

I/O 0

R/W

OE

tSD

DATAIN VALID

tSA

tPWE

tHD

DATAOUT VALID

WRITE CYCLE

tSWRD

tSOP

tDOE

READ CYCLE

A0L –A2L

Figure 10. Timing Diagram of Semaphore Contention[38, 39, 40]

MATCH

R/WL

SEM L

A 0R–A2R

R/WR

SEM R

tSPS

MATCH

Notes

37. CE = HIGH for the duration of the above timing (both write and read cycle).

38. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH.

39. Semaphores are reset (available to both ports) at cycle start.

40. If tSPS is violated, the semaphore is definitely obtained by one side or the other, but which side gets the semaphore is unpredictable.

Document #: 38-06035 Rev. *D

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