CY7C0241-25AXC View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C0241-25AXC

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

Cypress Semiconductor 

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CY7C024/024A/0241

CY7C025/0251

Switching Waveforms (continued)

Figure 13. Busy Timing Diagram No.1 (CE Arbitration)[42]

CELValid First:

ADDRESS L,R

ADDRESS MATCH

CEL

CER

BUSYR

CER Valid First:

ADDRESS L,R

tPS

tBLC

tBHC

ADDRESS MATCH

CER

CE L

BUSYL

tPS

tBLC

tBHC

Figure 14. Busy Timing Diagram No.2 (Address Arbitration)[42]

Left Address Valid First:

ADDRESS L

tRC or tWC

ADDRESS MATCH

tPS

ADDRESS MISMATCH

ADDRESSR

BUSY R

tBLA

tBHA

Right Address Valid First:

ADDRESSR

ADDRESSL

BUSY L

tRC or tWC

ADDRESS MATCH

tPS

tBLA

ADDRESS MISMATCH

tBHA

Note

42. If tPS is violated, the busy signal is asserted on one side or the other, but there is no guarantee to which side BUSY is asserted.

Document #: 38-06035 Rev. *D

Page 15 of 21

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