CY7C0241-25AXC View Datasheet(PDF) - Cypress Semiconductor

Part Name

Description

MFG CO.

CY7C0241-25AXC

4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, BUSY

Cypress Semiconductor 

1 2 3 4 5 6 7 8 9 10 Next

CY7C024/024A/0241

CY7C025/0251

Logic Block Diagram

L

L

L

OE L

R/WR

UBR

LBR

CER

OE R

[4]

I/O 8L – I/O 15L

I/O

0L

–

I/O

[3]

7L

[2]

BUSYL

(CY7C025/0251) A12L

A11L

A0L

Pin Configurations

R/W L

SEM L

INT L

I/O

CONTROL

I/O

CONTROL

ADDRESS

DECODER

MEMORY

ARRAY

ADDRESS

DECODER

CE L

OE L

UB L

LB L

INTERRUPT

SEMAPHORE

ARBITRATION

M/S

CE R

OE R

UB R

LB R

Figure 1. 84-Pin PLCC (Top View)

I/O8R – I/O15R[4]

I/O

0R–

I/O

[3]

7R

[2]

BUSYR

A12R (CY7C025/0251)

A11R

A 0R

R/W R

SEM R

INTR

I/O8L

I/O9L

I/O10L

I/O11L

I/O12L

I/O13L

GND

I/O14L

I/O15L

VCC

GND

I/O0R

I/O1R

I/O2R

VCC

I/O3R

I/O4R

I/O5R

I/O6R

I/O7R

I/O8R

11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75

74

12

73

13

72

14

71

15

70

16

69

17

68

18

67

19

66

20

21

CY7C024/024A/025

65

64

22

23

63

24

62

25

61

26

60

27

59

28

58

29

57

56

30

31

55

54

32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53

A7L

A6L

A5L

A4L

A3L

A2L

A1L

A0L

INTL

BUSYL

GND

M/S

BUSYR

INTR

A0R

A1R

A2R

A3R

A4R

A5R

A6R

Notes

2. BUSY is an output in master mode and an input in slave mode.

3. I/O0 –I/O8 on the CY7C0241/0251.

4. I/O9 –I/O17 on the CY7C0241/0251.

5. A12L on the CY7C025/0251.

6. A12R on the CY7C025/0251.

Document #: 38-06035 Rev. *D

Page 2 of 21

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