CY7C0241-25AXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY7C0241-25AXC
Cypress Semiconductor
'CY7C0241-25AXC' PDF : 21 Pages View PDF
CY7C024/024A/0241
CY7C025/0251
Switching Characteristics Over the Operating Range [14]
Parameter
Description
7C024/024A/0241–15 7C024/024A/0241–25 7C024/024A/0241–35 7C024/024A/0241–55
7C025/0251–15
7C025/0251–25
7C025/0251–35
7C025/0251–55 Unit
Min
Max Min
Max
Min
Max
Min
Max
Read Cycle
tRC
Read Cycle Time
15
25
35
55
ns
tAA
Address to Data Valid
15
25
35
55 ns
tOHA
Output Hold From Address
3
3
3
3
ns
Change
tACE[15]
CE LOW to Data Valid
15
25
35
55 ns
tDOE
OE LOW to Data Valid
tLZOE[16, 17, 18] OE Low to Low Z
tHZOE[16, 17, 18] OE HIGH to High Z
tLZCE[16, 17, 18] CE LOW to Low Z
tHZCE[16, 17, 18] CE HIGH to High Z
tPU[18]
CE LOW to Power Up
tPD[18]
CE HIGH to Power Down
tABE[15]
Byte Enable Access Time
10
13
20
25 ns
3
3
3
3
ns
10
15
20
25 ns
3
3
3
3
ns
10
15
20
25 ns
0
0
0
0
ns
15
25
25
55 ns
15
25
35
55 ns
Write Cycle
tWC
Write Cycle Time
15
25
35
55
ns
tSCE[15]
CE LOW to Write End
12
20
30
35
ns
tAW
Address Setup to Write End
12
20
30
35
ns
tHA
Address Hold From Write End 0
0
0
0
ns
tSA[15]
Address Setup to Write Start
0
0
0
0
ns
tPWE
Write Pulse Width
12
20
25
35
ns
tSD
Data Setup to Write End
10
15
15
20
ns
tHD
Data Hold From Write End
0
0
0
0
ns
tHZWE[17, 18] R/W LOW to High Z
10
15
20
25 ns
tLZWE[17, 18] R/W HIGH to Low Z
0
0
0
0
ns
tWDD[19]
Write Pulse to Data Delay
30
50
60
70 ns
tDDD[19]
Write Data Valid to Read
Data Valid
25
35
35
45 ns
Notes
14. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOI/IOH
and 30 pF load capacitance.
15. To access RAM, CE=L, UB=L, SEM=H. To access semaphore, CE=H and SEM=L. Either condition must be valid for the entire tSCE time.
16. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE.
17. Test conditions used are Load 3.
18. This parameter is guaranteed but not tested.
19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Figure 11.
Document #: 38-06035 Rev. *D
Page 9 of 21
[+] Feedback
Share Link: 