CY8C20111, CY8C20121
OUTPUT_STATUS
Output Status Register
OUTPUT_STATUS: 00h
1 Button
7
6
5
4
3
2
1
0
Access: FD
R:01
Bit Name
STS[0]
2 Button
7
6
5
4
3
2
Access: FD
Bit Name
The Output Status register represents the actual logical levels on the output pins.
Bit
Name
1:0
STS [1:0]
Description
Used to represent the output status
0 Output low
1 Output high
OUTPUT_PORT
Output Port Register
OUTPUT_PORT: 04h
1 Button
7
6
5
4
3
2
Access: FD
Bit Name
1
0
R:03
STS[1:0]
1
0
W:01
DIG[0]
2 Button
7
6
5
4
3
2
1
0
Access: FD
W:03
Bit Name
DIG[1:0]
This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be
changed using this register.
Bit
Name
1:0
DIG [1:0]
Description
A bit set in this register sets the logic level of the output.
0 Logic ‘0’
1 Logic ‘1’
CS_ENABLE
Select CapSense Input Register
CS_ENABLE: 07h
(Writable only in Setup mode)
1 Button
7
6
5
4
3
2
1
0
Access: FD
RW:01
Bit Name
CS[0]
2 Button
7
6
5
4
3
2
1
0
Access: FD
RW:03
Bit Name
CS[1:0]
Document Number: 001-53516 Rev. *H
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