CY8C20111 View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
CY8C20111
Cypress Semiconductor
'CY8C20111' PDF : 34 Pages View PDF
CY8C20111, CY8C20121
OP_SEL_x
Logic Operation Selection Registers
OP_SEL_0: 1Ch
OP_SEL_1: 21h (Not available for 1 Button)
1/2Button
7
6
5
4
3
2
1
0
Access: FD
RW: 0
RW: 0
RW: 0
Bit Name
Op_En
InvOp
Operator
This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on
DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not
have any effect.
The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output
of logic operation can also be inverted.
Bit
Name
7
Op_En
1
InvOp
0
Operator
Description
This bit enables or disables logic operation.
0 Disable logic operation
1 Enable logic operation
This bit enables or disables logic operation output inversion.
0 Logic operation output not inverted
1 Logic operation output inverted
This bit selects which operator should be used to compute logic operation.
0 Logic operator OR is used on inputs
1 Logic operator AND is used on inputs
LOGICAL_OPR_INPUTx
Selects Input for Logic Operation
LOGICAL_OPR_INPUT0: 1Eh LOGICAL_OPR_INPUT1: 23h (Not available for 1 button)
LOGICAL_OPR_INPUT0
1 Button
7
6
5
4
3
2
Access: FD
Bit Name
1
0
RW:01
CSL[0]
2 Button
7
6
5
4
3
2
1
0
Access: FD
RW:01
Bit Name
CSL [1:0]
LOGICAL_OPR_INPUT1
2 Button
7
6
5
4
3
2
1
0
Access: FD
RW:02
Bit Name
CSL [1:0]
These registers are used to give the input to logic operation block. The inputs can be only CapSense input status.
Bit
Name
1:0
CSL [1:0]
Description
These bits selects the input for logic operation block.
Document Number: 001-53516 Rev. *H
Page 15 of 44
Share Link: 