CYW15G0401DXB-BGXC View Datasheet(PDF) - Cypress Semiconductor
Part Name
Description
MFG CO.
'CYW15G0401DXB-BGXC' PDF : 53 Pages View PDF
CYP15G0401DXB
CYV15G0401DXB
CYW15G0401DXB
Transmit Path Block Diagram
REFCLK+
REFCLK–
TXRATE
SPDSEL
TXCLKO+
TXCLKO–
TXMODE[1:0]
2
TXCKSEL
TXPERA
SCSEL
TXDA[7:0] 8
Transmit PLL
Clock Multiplier
Character-Rate Clock
Transmit
Mode
12
12
TXOPA
TXCTA[1:0] 2
TXCLKA
TXPERB
HML
TXDB[7:0] 8
TXOPB
TXCTB[1:0] 2
11
11
HML
TXCLKB
TXPERC
TXDC[7:0] 8
TXOPC
TXCTC[1:0] 2
11
11
HML
TXCLKC
TXPERD
TXDD[7:0] 8
TXOPD
TXCTD[1:0]
11
11
HML
TXCLKD
TXRST
PARCTL
Bit-rate Clock
= Internal Signal
Character-Rate Clock
BISTLE
BIST Enable
Latch
4
12
10
Output
Enable
Latch
8
BOE[7:0]
RBIST[D:A]
OELE
OUTA1+
OUTA1–
OUTA2+
OUTA2–
TXLBA
12
10
OUTB1+
OUTB1–
OUTB2+
OUTB2–
TXLBB
12
10
OUTC1+
OUTC1–
OUTC2+
OUTC2–
TXLBC
12
10
OUTD1+
OUTD1–
OUTD2+
OUTD2–
TXLBD
Parity Control
Document #: 38-02002 Rev. *L
Page 4 of 53
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